Q2. Consider a 4-way set associative cache. Suppose that the 3 pseudo-LRU bits f
ID: 3710128 • Letter: Q
Question
Q2. Consider a 4-way set associative cache. Suppose that the 3 pseudo-LRU bits for set 7 are 001 and the set is currently full. The next memory reference that maps to set 7 is a write miss. The pseudo-LRU bits are described in module 9 material.
a) (5) Assuming a write-allocate policy is used, which line (way0, way1, way2 or way3) within set 7 should be replaced in response to the write miss?
b) (5) Suppose that the reference to set 7 had instead caused a hit in way2, and that the three pseudo-LRU bits for set 7 were 001 before the reference. What would the three pseudo-LRU bits be after the reference is made?
Explanation / Answer
In 4-way set associative cache LRU bits are used to identify the block/line in cache to be replaced on a miss or to indicate which block/line is least recently used.
'0' indicates least recently used and '1' indicates most recently used.
a) In LRU bits- 001, the first left most '0' bit indicates that, line way0,way1 are least recently used than the lines way2 and way3.
the second '0' bit indicates, line way0 is least recently used than line way1.
Therefore, upon a write miss, the line way0 which is least recently used is replaced in response to write miss.
b) Suppose it is a hit in way2 and LRU bits are 001 before reference in line way2, to indicate that line way2 is most recently used, the first left most bit should be made '0' so that on next miss, lines way0 or way1 will get selected based on the second left most bit which remains unchanged. The last right most bit is made to '1'.
Thus the three pseudo-LRU bits will become as 001.
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