2. Assume a memory hierarchy with separate data and instruction memories. The mi

Question

2. Assume a memory hierarchy with separate data and instruction memories. The miss rate of data cache is equal to 12%, miss penalty equal to 100 cycles. The miss rate of instruction cache is equal to 7%. miss penalty equal to 100 cycles, 25% of the instructions are Load/Store instructions. The TLB miss rate per TLB access equal to 5% and TLB miss penalty equal to 80 cycles. What is the realistic CPl of this system if the ideal CPI is 2.1? What is the speedup compared to not having TLB? What would be the speedup if the TLB could hold every entry?

Explanation / Answer

Instruction-cache miss rate = 3%

Data-cache miss rate = 4%

Miss penalty = 30

Base CPI = 1.0

Load and Stores are 45% of instructions

Now,Miss cycles per instruction:

Instruction-cache = 0.03 * 30= 0.90

Data-cache = 0.04 0.45 30 = 0.54

Actual CPI = 1 + 0.90 + 0.54 = 2.44

Ideal CPU is 2.44/2 = 1.22 times faster (Average CPI)

We spend 1.44/2.44 = 59% of our execution time on memory stalls

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