Q3 A block diagram of 1-bit ALU is given below. Note that, in this implementatio

Question

Q3 A block diagram of 1-bit ALU is given below. Note that, in this implementation, a 2-1 MUX is used to invert the bits for SUB operation. Another 3-1 multiplexer is used to select one of the 3 outputs from an AND gate, OR gate and Full Adder based on the given Opcode (table is given) The block diagram of the smallest MUX in the diagram is given below. The specification of this MUX is F b-invert ? B 8 [ that is, if (b-invert) B'ELSE F B 1. b-invert Draw a circuit for this 2-1 MUX. The control codes (Opcodes) for the 3-1 MUX is given below Draw a circuit diagram for the required 3-1 MUX using two 2-1 MUXs. Opcode Operation and 01 or add

Explanation / Answer

Good evening

In the question they given that we have to use 2 to one MUX instead of 3 to one MUX

So we introduce one new MUX that takes the input from the OR and AND gates then result is send it to the final MUX that final MUX takes the another input from the ader.

(Required Circuit diagram is I uploaded above already)

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