Exercise 1: (12 pts) How many memory chips are required to construct 8M X 32 mem

Question

Exercise 1: (12 pts) How many memory chips are required to construct 8M X 32 memory using 512K X 8 chip? A 2M x 32 memory uses coincident decoding by splitting the internal decoder to row-selection and column-selection. Determine the row and column lines enabled when the input address is (4328)10 A 256K X 16 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select, (a) Assuming that the RAM cell array is square, what is the size of each decoder, and how many AND gates are required for decoding an address?

Explanation / Answer

So, number of memory chips required to make (8M x 32) using (512K x 8) is

=(8 x 1024 x 32) / (512 x 8) = 64

2. 4328 is x10E8 in hex.

So, the first ten bits are 0001 0000 11 or 43.

So, 43 is the row decoder output which will be enabled.

3. The memory has 1M = 1024k = 1024 x 1024

So, it has 1024 rows and columns. That means the row decoder will require 10 bits(as 1024 = pow(2,10)). So we can understand that it is a 10-to-1024 decoder.

Since the memory has 256K= (256 x 1024 x 1024) = pow(2,18) words. So, it will be needed 18 address bits overall. So, the column decoder will use 6 bits and which is an 8-to-256 decoder. The column decoder has 1024 outputs. So, it can be implemented with 1024 AND gates with 10 input each. The columns are 8-to-256 decoders, so these will each have 256 AND gates. But there are 18 for the input and also 18 multiplexors for the outputs, so it will be 1024+(256 x 18)=5632 AND gates for the column decoding. And the size of each decoder is 8 to 256.

Where, pow(2,10) = 2 to the power of 10.

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