Problem 5 (16 points. Suggested time: 15 mins) Part a (4 points): (Fill in the b

Question

Problem 5 (16 points. Suggested time: 15 mins) Part a (4 points): (Fill in the blanks) Recall that the instruction cyele in the sequential implementation of a processor consists of six phases, not all of which are needed by all instructions. However, all instructions do need the stage and the stage. Part b (6 points): Consider the following combinational circuit, where the logic block A takes 100 ns, B takes 100 ns, C takes 200 ns, and D takes 100 ns; also assume that it takes 20 ns to load data into a register Input(100 ns) (100 ns) Output (200 ns (3 points) What is the latency of this circuit from input to output? (3 points) What is the overall throughput of this circuit? Part e (6 points): A student who just took CSC 252 came up with a pipelined implementation. She used two additional pipeline registers, and the new design is shown below. All the registers are connected to the clock signal, which is omitted in this figure for simplicity purpose.

Explanation / Answer

Part(a)

The two stages that are important in the sequential implementation of a processor are the Fetch stage and the execute stage.

Part (b)

In the given circuit, the time taken will be the time taken by the longest path, here, longest path is

A ==> C ==> D

time taken = 100 + 200 + 100+ 20 = 420 ns

Each time, the output will be delayed by 100 ns due to difference in time taken by C and B,

Throughput = 320/420 = 0.7619

Part (c)

In the given circuit, the time taken will be the time taken by the longest path, here, longest path is

A ==> C ==> D

time taken = 100 + 200 + 20 + 100+ 20 = 440 ns

Each time, the output will be delayed by 100 ns due to difference in time taken by C and B,

Throughput = 340/440 = 0.7727

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