Design a toy CPU which needs to execute various instructions like: ADD RI ??? AN

Question

Design a toy CPU which needs to execute various instructions like: ADD RI ??? AND RI . OR RI MOV R1, R2 MOV R2, Rl MOV R1. ACC MOV R2, ACOC . MOV ACC, RI MOV ACC, R2 MVI RI, #33H MOV M, ACC MOV ACC, M *JMP . STA 5000M I/Getting the contents at 6000M location into the accumulator . LDA 6000M //Store the contents of accumulator at 6000M location You need to * Design the data path (as shown in slide 5/6/16, on the project chapter). . Decide the instruction format o o o How many bits for the instruction How many bits for the opcode How many bits for the operand - Need to specify various micro-instructions (and the machine states) for each of the above nstructions Generate various control signals for micro-operations o You need to explain each of the CPU o Explain how data flows o Each instruction should be analyzed in detail. components in detail

Explanation / Answer

In planning a guideline set, the accompanying contemplations are require:

    Instruction length
    Number of operands
    Memory organization
    Addressing modes.

Given framework has 16 registers. Along these lines, it needs 4 bits to get to one of the registers and furthermore it needs 12 bits for a memory address. On the off chance that the framework is to have 16-bit guidelines, at that point there are two decisions for our directions.

In the event that the length of the opcode to differ, the accompanying guideline sets can be made:

0 0 0 0 R1 R2 R3

1 1 1 0 R1 R2 R3

15, 3-address code

1 1 1 1 0 0 0 0 R1 R2

1 1 1 1 1 1 0 1 R1 R2

14, 2-address code

1 1 1 1 1 1 1 0 0 0 0 0 R2

1 1 1 1 1 1 1 1 1 1 1 0 R1

31, 1-address code

1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0

1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1

16, 0-address code

Operation Op Code Destination Register Source Register Target Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADD 0 0 0 0 Rd Rs Rt SUB 0 0 0 1 Rd Rs Rt AND 0 0 1 0 Rd Rs Rt OR 0 0 1 1 Rd Rs Rt XOR 0 1 0 0 Rd Rs Rt

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