(c) Consider a processor with 32 bit virtual addresses, 4K-byte pages, and 36-bi
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(c) Consider a processor with 32 bit virtual addresses, 4K-byte pages, and 36-bit physical addresses. Assume el memory is byte-addressable. . LI data cache 32K by 4-byte blocks, 2-way set associative, indexed and tagged with physical address, write-bac . 4-way set associative TLB with 128' entries in all. Assume the TLB keeps a valid bit, a dirty bit, a reference bit, and three permission bits (read, write, execute) for each entry Specify the number of byte offset, index, and tag bits for data cache and the size of each field of a TLB (13) entryExplanation / Answer
c) Size of virtual address = 32 bit
Page size = Frame size = 4K byte = 212 byte.
Physical address size =36 bit.
Size of data cache = 32 K byte = 215 byte.
Size of each block in the data cache = 64 byte = 26 byte.
Therefore number of blocks in the cache = Size of data cache/ Size of each block in the data cache = 215/26 = 29 .
As the cache is 2 way set associative so, the number of blocks per set = 2
Therefore number of sets in the data cache = 29/2 = 28 .
Therefore number of index bits for the data cache = 8.
As page size is 212 byte so, number of bits in the byte offset field of data cache is = 12.
As the cache is physically addressed we will use the physical address( 36 bits) here:
Therefore number of bits in the tag field of data cache = 36 - 12 - 8 = 16.
As page offset is 12 bits , with a 32-bit virtual address, this leaves 20 bits to index a set in the TLB and tag entries in that set. Since the TLB has 128 entries and each set has 4 entries (4-way associative), there are 32 sets, requiring 5 bits to index a set. This leaves 15 bits for the tag in TLB.
The size of the physical page number in the TLB is equal to the size of the physical address minus the size of the page offset: 36 - 12 = 24 bits.
The rest fields in the TLB entry are a valid bit , a dirty bit, a reference bit and three permission bits.
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