Instructor: Ahmad Lashgar, PhD March 19, 2018 Columbia College ancouwer, Conads

Question

Instructor: Ahmad Lashgar, PhD March 19, 2018 Columbia College ancouwer, Conads 1. For a directmapped cache design with 32-bit address, the following bits of the address are used to access the cache Index Byte offset 31-10 9-4 3-0 a) What is the cache line size in bytes? b) How many entries does the cache have? c) What is the ratio between total bits required (data, tag, and valid bits) over the data storage bits? Starting from power on (empty cache), the following byte addressed cache references are recorded: Address #1>0 Address #2>4 Address #3216 Address #4>132 Address #5> 232 Address #6> 160 Address #7> 1024 Address #8>30 Address #9> 140 Address #10> 3100 Address #11> 180 Address #12> 2180 d) How many blocks are replaced? e) What is the hit ratio? f) List the final state of the cache, with each valid entry represented as a record of

Explanation / Answer

a) cache line size in bytes = 2^N bytes [where N= no of offset bits]

=2^4= 16 bytes

cache line size in words= 2^N-2

=2^(4-2)= 2^2 = 4 words

b) no of cache enteries= 2^(no of index bits)

=2^6 = 64

c) no of bytes for tag field= (64*22)/8= 176 bytes

size of cache= 2^10 bytes

total bits for cache= 1024+176= 1200 bytes

rato= 1200/4096= 0.29

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