Build a Verilog module named \"calculator\" that takes in two signed 16-bit numb
ID: 3692498 • Letter: B
Question
Build a Verilog module named "calculator" that takes in two signed 16-bit numbers named "in1" and "in2" and performs the following functions depending on the value of another 4-bit input named "opCode" (see table below). Be aware that the opCode is not signed like the inputs A and B of project 2 were. The outputs of the module "calculator" must be a signed 16-bit number named "result", and a 1-bit "overflow". Be aware that the value of "overflow" doesn't always get calculated the same way, it depends on the operation (see table below for more info and examples). The value of the output "overflow" will be one if an overflow occurred or the value of "result" is not completely accurate or correct; else the output "overflow" will be zero.
The syntax to declare buses as signed is:
input signed [15:0] in1;
output reg signed [15:0] result;
//Declaring outputs as "reg" will allow you to assign values to them
Also, be aware that unsigned N-bit registers can store values from 0 to 2N-1. While signed N-bit registers can store values from -2N-1 to 2N-1-1.
Your test bench:
Your test bench must show a good effort in testing. You must test all the opCodes. Test when in1 is positive and when it is negative, and when in2 is positive and when it is negative. Test values that produce overflow, and also values that don't produce overflow. Also, pay attention to interesting values, like border (or corner) cases, like: 32767, 32766, 1, 0, -1, -32767, -32768.
There must be minimum 23 test cases covering these scenarios:
one test per bitwise operation,
two test cases (one not producing overflow and another producing overflow) for each of the operations of:
increment,
decrement
divide
four test cases for multiplication:
one not producing overflow when in1 is positive
one not producing overflow when in1 is negative,
one producing overflow when the result is too positive
one producing overflow when the result is too negative
six test cases for addition:two test cases that produce overflow:
one producing overflow when the result is too positive
one producing overflow when the result is too negative
four test cases that don't produce overflow:
one where in1 is positive and in2 is positive
one where in1 is positive and in2 is negative
one where in1 is negative and in2 is positive
one where in1 is negative and in2 is negative
six test cases for subtraction:two test cases that produce overflow:
one producing overflow when the result is too positive
one producing overflow when the result is too negative
four test cases that don't produce overflow:
one where in1 is positive and in2 is positive
one where in1 is positive and in2 is negative
one where in1 is negative and in2 is positive
one where in1 is negative and in2 is negative
Include in your test bench a $monitor statement in order to keep track and print in console changes in the inputs and outputs. Alternatively you could have $display statements instead. For example:
$monitor("opCode( %b ), in1( %d ), in2( %d ), result( %d ), overflow( %b )", opCode, in1, in2, result, overflow);
opCode Operation that has to be performed (bold alternates to separate operations) 0000 Add both inputs. Be aware that the overflow detection when adding and subtracting must be different than for Project 2 because in Project 2 the inputs were unsigned, while now for Project 3 the inputs are signed. 0001 Subtract in1 - in2. 0010 Multiply in1 by five 0011 Divide in1 by ten. When dividing by ten, signal an overflow when in1 is not exactly divisible by ten. For instance, if in1=30, then result=3 and overflow=0; but if in1=35, then result=3 and overflow=1. You will need to explore the use of the percentage sign (%), which performs modulo operations (also known as "modulus operator", https://en.wikipedia.org/wiki/Modulo_operation ). The modulo finds the remainder of a division. If the remainder is zero then overflow=0; but if the remainder is not zero then produce overflow =1. 0100 Bitwise AND. Even though in1, in2 and result are declared as signed numbers, when applying the bitwise operations they are taken as raw bits. A bitwise operation (https://en.wikipedia.org/wiki/Bitwise_operation ) is when the operation is applied to the individual bits. In this case, there will be an AND gate operation between the individual bits of in1 and the individual bits of in2; such that an AND logic will be applied to the first bit of in1 and the first bit of in2 and the output of that AND will be the first bit of result; an AND logic will be applied to the bit of position n of in1 and the bit of position n of in2 and the output of that AND will be the bit of position n of result; and so on.For example:
in1 = 1010110011110000
in2 = 1100101000110011
result = 1000100000110000
Bitwise AND, XOR and OR operations can't overflow, so overflow=0 by default. 0101 Bitwise XOR. Similar to explanation above, but with an XOR (also known as exclusive OR) operation instead.
Example:
in1 = 1010110011110000
in2 = 1100101000110011
result = 0110011011000011 0110 Bitwise OR. Similar to explanation above, but with an OR operation instead.
Example:
in1 = 1010110011110000
in2 = 1100101000110011
result = 1110111011110011 0111 One's Complement in1. Perform one's complement, by inverting bits (do not add one afterwards, because that would be two's complement). Complement operation can't overflow, so overflow=0 by default.
Examples:
in1='b00000000000000; opCode='b0111; expectedOverflow='b0; result='b1111111111111111;
in1='b0000000000000001; opCode='b0111; expectedOverflow='b0; result='b1111111111111110; 1000 Increment in1 by 1.
Examples:
if in1=3, then result =4.
if in1=-3, then result =-2. 1001 Decrement in1 by 1.
Examples:
if in1=3, then result =2
if in1=-3, then result =-4.
Explanation / Answer
module Calculator(in1,in2,opCode,result,overflow);
input signed[15:0] in1, in2;
input[3:0] opCode;
output reg signed[15:0] result;
output reg overflow;
always @ (*) begin
if(opCode == 0000) begin
if(in1+in2<=32767 & in1+in2>= -32768) begin
overflow = 0;
end
else
begin
overflow = 1;
end
end
end
always @ (*) begin
if(opCode == 0001) begin
if(in1-in2<=32767 & in1-in2>= -32768) begin
overflow = 0;
end
else
begin
overflow = 1;
end
end
end
always @ (*) begin
if(opCode == 0010) begin
if(in1*5<=32767 & in1*5>= -32768) begin
overflow = 0;
end
else
begin
overflow = 1;
end
end
end
always @ (*) begin
if(opCode == 0011) begin
if ((in1 % 10) == 0) begin
overflow = 0;
end else begin
overflow = 1;
end
end
end
always @ (*) begin
if(opCode == 0100) begin
overflow = 0;
end
end
always @ (*) begin
if(opCode == 0101) begin
overflow = 0;
end
end
always @ (*) begin
if(opCode == 0110) begin
overflow = 0;
end
end
always @ (*) begin
if(opCode == 0111) begin
overflow = 0;
end
end
always @ (*) begin
if(opCode == 1000) begin
if(in1 == 32767) begin
overflow = 1;
end
else begin
overflow = 0;
end
end
end
always @ (*) begin
if(opCode == 1001) begin
if(in1==-32768) begin
overflow = 1;
end
else
begin
overflow = 0;
end
end
end
always @ (*) begin
case(opCode)
4'b0000: result = in1+in2; //add
4'b0001: result = in1-in2; //subtract
4'b0010: result = in1*5; //mult by 5
4'b0011: result = in1/10; //divide by 10
4'b0100: result = in1&in2; //AND
4'b0101: result = in1^in2; //XOR
4'b0110: result = in1|in2; //OR
4'b0111: result = /*((2^16)-1)-in1;*/(-(in1))-1; //complement
4'b1001: result = in1-1; //decrement
4'b1000: result = in1+1; //increment
endcase
end
endmodule
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.