A snooping cache coherence protocol is implemented such as the one discussed in
ID: 3690332 • Letter: A
Question
A snooping cache coherence protocol is implemented such as the one discussed in class, in a symmetric shared-memory multiprocessor with 3 processors sharing a bus, Describe the steps of the coherence protocol mentioning the eventual state of the data block in the caches of each of the 3 processors for each of the instructions below. Note that the caches are direct-mapped and that each cache block only stores one word and words X and Y map to the same cache block in each cache (i.e. X and Y can’t be both in the cache at the same time). Assume that at the beginning X and Y are not in any of the caches.
P1: Write X
P1: Read X
P2: Write X
P3: Read X
P1: Read X
P2: Write X
P1: Read Y
P2: Read X
Event Status P1 Status P2 Status P3 Bus SAS A ActionProcAddr ProcAddrExplanation / Answer
Alignment is not comming properly if u have any queries please comment
Event Status P1 Status P2 Status P3 Bus
S A S A S A Action Proc Addr
P1 write X Excl x WrMiss P1 x
P1 Read X Excl x
P2 write X Invalid x Excl x WrMiss P2 x
WrBk P1 x
RdData P2 x
P3 Read X Shared x Share d x RdMiss P3 x
WrBk P2 x
RdData P3 x
P1 Read X Shared x Shared x Share d x Rdmiss P1 x
RdData P1 x
P2 WriteY Shared x Excl y Share d x WrMiss P2 y
RdData P2 y
RdMiss P1 y
P1 Read Y shared y Shared y Share d x RdMiss P1 y
WrBk P2 y
RdData P1 y
P2 Read X Shared y Shared x Shared d x RdMiss P2 x
RdData P2 x
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