Wanted to verify myself on these two questions 1) Learning how to code a decoder
ID: 3688811 • Letter: W
Question
Wanted to verify myself on these two questions
1) Learning how to code a decoder in Verilog:
Complete the code of the following Verilog module that implements a decoder that receives a 3-bit input named "W" and produces a 7-bit output named "display" . This decoder converts from binary (value contained in 'W') to seven-segment display format the numbers zero, one and two; and signals overflow for any other value:
module decoder(
input[2:0] W // W is 3 bits long
output reg[ _________:0] display// is 7 bits long
);
always @ (W) begin
case(_______________)
3'b000: display= 7'b1111110;//0
____________: display = 7'b0110000; // 1
3'b010: display= _________________; // 2
default: display = 7'b0011101; // 'o' as in overflow
endcase
end
endmodule
NOTE: There are 4 total blanks that need to be filled in.
2)
Muxes, also known as Multiplexers, are sometimes called selectors because they select one input to pass through to the output.
One of the recommended resources mentioned in the instructions file of project 2 shows 3 different ways to code a mux in Verilog. Please study them: http://www.asic-world.com/examples/verilog/mux.html
In the examples, "sel" would be equivalent to S in project 2; "din_1" would be the result (including overflow) of the addition; and "din_0" would be the result (including overflow) of the subtraction.
Please complete the Verilog code of the following modules, such that they are equivalent to this schematic:
module mux_using_assign(
input S,
input X,
input Y,
output Z
);
assign Z = (________) ? X|Y : ___________;
endmodule
-------------------------------------
module mux_using_if(
input S,
input X,
input Y,
output Z
);
___________ Z;
always @ ( _________ ) begin : MUX
if (___________ == 1'b1) begin
Z = X|Y;
end else begin
Z = ____________ ;
end
end
endmodule
-------------------------------------
module mux_using_case(
input S,
input X,
input Y,
output Z
);
______________ Z;
always @ ( ___________ )begin : MUX
case(_____________)
1'b0 : Z = _____________;
______________: Z = X|Y;
endcase
end
endmodule
NOTE: 11 blanks in total for part 2
Thanks, in advance, for any feedback! I really appreciate it.
Explanation / Answer
Question 1:
module decoder(
input[2:0] W // W is 3 bits long
output reg[ _7_:0] display// is 7 bits long
);
always @ (W) begin
case(_W_)
3'b000: display= 7'b1111110;//0
_3'b001_: display = 7'b0110000; // 1
3'b010: display= _7'b1101101_; // 2
default: display = 7'b0011101; // 'o' as in overflow
endcase
end
endmodule
Question 2:
module mux_using_assign(
input S,
input X,
input Y,
output Z
);
assign Z = (_S_) ? X : _Y_;
endmodule
-------------------------------------
module mux_using_if(
input S,
input X,
input Y,
output Z
);
_REG_ Z;
always @ ( _S OR Y OR X_ ) begin : MUX
if (_S_ == 1'b1) begin
Z = X|Y;
end else begin
Z = _Y_ ;
end
end
endmodule
-------------------------------------
module mux_using_case(
input S,
input X,
input Y,
output Z
);
_REG_ Z;
always @ ( _S OR X OR Y_ )begin : MUX
case(_S_)
1'b0 : Z = _X_;
_1'b1_: Z = X|Y;
endcase
end
endmodule
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.