During a 68000 memory read cycle, at which CLK edge does the processor test DTAC

Question

During a 68000 memory read cycle, at which CLK edge does the processor test DTACK* and decide whether to complete the memory cycle or to wait and retest DTACK* one CLK cycle later? (a) the rising edge of CLK at the end of state S3 (b) the falling edge of CLK at the end of state S4 (c) the rising edge of CLK at the end of state S5 (d) the falling edge of CLK at the end of state S6 (e) none of the above 4. During a 68000 memory read cycle, at which CLK edge does the processor capture the memory data from the data bus? (a) the rising edge of CLK at the end of state S3 (b) the falling edge of CLK at the end of state S4 (c) the rising edge of CLK at the end of state S5 (d) the falling edge of CLK at the end of state S6 (e) none of the above

Explanation / Answer

3.c

4.d

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