n this lab, a combinational VHDL process will be used to design a combinational
ID: 3686670 • Letter: N
Question
n this lab, a combinational VHDL process will be used to design a combinational integer to floating-point converter. The converter will have a single input which represents an signed 4-bit two’s complement integer and two outputs - an 8-bit output representing the integer value in a specific floating-point format and an output to indicate underflow situations (the input is a number less than 1, i.e. 0). Unlike the approach taken in Lab 3, we will not use a brute-force approach but solve the problem in a more elegant method making use of the VHDL variable. Use a VHDL process which counts the number of leading zeros present in the input and based on this number, determines the values of the mantissa and exponent fields and sign bit of the floating point format accordingly. The process should also perform the necessary negation of any inputs which correspond to negative integers. Hint: Should you use a signal or a variable to keep track of the number of leading zeros? Hint: Should you use a signal or a variable to perform the negation of any negative input values? signal keith : std_logic_vector(3 downto 0); begin process(keith) begin keith <= keith + “0001” ; -- is this good or bad ??? Another hint: Use a Boolean to determine when you have found the first 1 in the input and when the first 1 is found, stop counting 0s.
Explanation / Answer
About the Decimal to Floating-Point Converter
This is a decimal to binary floating-point converter. It will convert a decimal number to its nearest single-precision and double-precision IEEE 754 binary floating-point number, using round-half-to-even rounding (the default IEEE rounding mode). It is implemented with arbitrary-precision arithmetic, so its conversions are correctly rounded. It will convert both normal and subnormal numbers, and will convert numbers that overflow (to infinity) or underflow (to zero).
The resulting floating-point number can be displayed in ten forms: in decimal, in binary, in normalized decimal scientific notation, in normalized binary scientific notation, as a normalized decimal times a power of two, as a decimal integer times a power of two, as a decimal integer times a power of ten, as a hexadecimal floating-point constant, in raw binary, and in raw hexadecimal. Each form represents the exact value of the floating-point number.
Why Use This Converter?
This converter will show you why numbers in your computer programs, like 0.1, do not behave as you’d expect.
Inside the computer, most numbers with a decimal point can only be approximated; another number, just a tiny bit away from the one you want, must stand in for it. For example, in single-precision floating-point, 0.1 becomes 0.100000001490116119384765625. If your program is printing 0.1, it is lying to you; if it is printing 0.100000001, it’s still lying, but at least it’s telling you you really don’t have 0.1.
How to Use This Converter
Input
If you want to convert another number, just type over the original number and click ‘Convert’ — there is no need to click ‘Clear’ first.
Output
There are ten output forms to choose from:
(See here for more details on these output forms.)
There are two output flags:
Implementation
I wrote this converter from scratch — it does not rely on native conversion functions like strtod() or strtof() or printf(). It is based on the big integer based algorithm I describe in my article “Correct Decimal To Floating-Point Using Big Integers”.
XCvhd.1 Barrel Shifter
A barrel shifter is a combinational logic circuit with n data inputs, n data outputs, and a set of control inputs that specify how to shift the data between input and output. A barrel shifter that is part of a microprocessor CPU can typically specify the direction of shift (left or right), the type of shift (circular, arithmetic, or logical), and the amount of shift (typically 0 to n –1 bits, but sometimes 1 to n bits).
In this subsection we’ll look at the design of a 16-bit barrel shifter that does six different types of shifts, as specified by a 3-bit shift-mode input C[2:0]. A 4-bit shift-amount input S[3:0] specifies the amount of shift. For example, if C specifies a left-circular shift and the input word is ABCDEFGHIJKLMNOP (where each letter represents one bit), and S[3:0] is 0101 (5), then the output word is FGHIJKLMNOPABCDE.
The shift types for this example are listed in Table XCvhd-1—circular, logical, and arithmetic, each with directions left and right. Table XCvhd-2 on the next page is a behavioral VHDL program for a 16-bit barrel shifter that performs any of six different combinations of shift type and direction. As shown in the entity declaration, a 4-bit control input S gives the shift amount, and a 3-bit control input C gives the shift mode (type and direction). We used the std_logic_arith package and defined the shift amount S to be type UNSIGNED
so we could later use the CONV_INTEGER function in that package.
Notice that the entity declaration includes six constant definitions that establish the correspondence between shift modes and the value of C. Although we didn’t discuss it in Section 5.3, VHDL allows you to put constant, type,
barrel shifter
Shift Type Name Code Note Table XCvhd- 1
Left rotate
Lrotate
000
Wrap-around
Right rotate
Rrotate
001
Wrap-around
Left logical
Llogical
010
0 into LSB
Right logical
Rlogical
011
0 into MSB
Left arithmetic
Larith
100
0 into LSB
Right arithmetic
Rarith
101
Replicate MSB
Shift types and
codings for a barrel shifter.
library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
entity barrel16 is port (
DIN: in STD_LOGIC_VECTOR (15 downto 0); -- Data inputs
S: in UNSIGNED (3 downto 0); -- Shift amount, 0-15 C: in STD_LOGIC_VECTOR (2 downto 0); -- Mode control
DOUT: out STD_LOGIC_VECTOR (15 downto 0) -- Data bus output
);
constant Lrotate: STD_LOGIC_VECTOR := "000"; -- Define the coding of constant Rrotate: STD_LOGIC_VECTOR := "001"; -- the different shift modes constant Llogical: STD_LOGIC_VECTOR := "010";
constant Rlogical: STD_LOGIC_VECTOR := "011"; constant Larith: STD_LOGIC_VECTOR := "100"; constant Rarith: STD_LOGIC_VECTOR := "101";
end barrel16;
architecture barrel16_behavioral of barrel16 is subtype DATAWORD is STD_LOGIC_VECTOR(15 downto 0);
function Vrol (D: DATAWORD; S: UNSIGNED) return DATAWORD is
variable N: INTEGER; variable TMPD: DATAWORD; begin
N := CONV_INTEGER(S); TMPD := D;
for i in 1 to N loop
TMPD := TMPD(14 downto 0) & TMPD(15);
end loop; return TMPD;
end Vrol;
...
begin
process(DIN, S, C) begin
case C is
when Lrotate => DOUT <= Vrol(DIN,S); when Rrotate => DOUT <= Vror(DIN,S); when Llogical => DOUT <= Vsll(DIN,S); when Rlogical => DOUT <= Vsrl(DIN,S); when Larith => DOUT <= Vsla(DIN,S); when Rarith => DOUT <= Vsra(DIN,S); when others => DOUT <= DIN;
end case; end process;
end barrel16_behavioral;
Synthesis:
->optimize .work.CSA_8.CSA -target xis2 -chip -area -effort standard -hierarchy auto Using wire table: xis215-6_avg
Pass
Area
Delay
DFFs
PIs POs --CPU--
(LUTs)
(ns)
min:sec
1
16
9
0
24
18
00:00
2
16
9
0
24
18
00:00
3
16
9
0
24
18
00:00
4
16
9
0
24
18
00:00
Info, Pass 1 was selected as best.
->optimize_timing .work.CSA_8.CSA Using wire table: xis215-6_avg
-- Start timing optimization for design .work.CSA_8.CSA No critical paths to optimize at this level
Info, Command 'optimize_timing' finished successfully ->report_area -cell_usage -all_leafs
Cell: CSA_8 View: CSA Library: work
*******************************************************
Cell
Library
References
Total Area
GND
xis2
1 x
1
1 GND
IBUF
xis2
24 x
1
24 IBU
LUT3
xis2
16 x
1
16 Function Generators
OBUF
xis2
18 x
1
18 OBUF
Number of ports :
42
Number of nets :
83
Number of instances :
59
Number of references to this view :
0
Total accumulated area :
Number of Function Generators :
16
Number of GND :
1
Number of IBUF :
24
Number of OBUF :
18
Number of gates :
16
Number of accumulated instances :
59
***********************************************
Device Utilization for 2s15cs144
***********************************************
Resource
Used
Avail Utilization
-----------------------------------------------
IOs
42
86
48.84%
Function Generators 16
384
4.17%
CLB Slices
8
192
4.17%
Dffs or Latches
0
672
0.00%
-----------------------------------------------
Critical Path Report
For Frequency = 50 Mhz
Critical path #1, (path slack = 11.5):
NAME
GATE
ARRIVAL
LOAD
------------------------------------------------------------------------------
b(7)/
0.00
0.00 up
1.90
b(7)_ibuf/O
IBUF
1.85 1.85 up
2.10
sm_dup0(8)/O
LUT3
1.57 3.42 up
2.10
sm(8)_obuf/O
OBUF
5.10 8.52 up
1.90
sm(8)/
0.00
8.52 up
0.00
data arrival time
8.52
data required time
(default specified)
20.00
------------------------------------------------------------------------------
data required time
20.00
data arrival time
8.52
----
slack
11.48
Critical path #2, (path slack = 1.5):
For Frequency = 100 MHz
data required time (default specified)
10.00
data required time
10.00
data arrival time
8.52
--------------------------------------------------------------------
slack
1.48
Left rotate
Lrotate
000
Wrap-around
Right rotate
Rrotate
001
Wrap-around
Left logical
Llogical
010
0 into LSB
Right logical
Rlogical
011
0 into MSB
Left arithmetic
Larith
100
0 into LSB
Right arithmetic
Rarith
101
Replicate MSB
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