Type and attach a Verilog^1 module to do the following: Input a 4-bit data word,

Question

Type and attach a Verilog^1 module to do the following: Input a 4-bit data word, Generate an 8-bit Hamming Code codeword by adding check bits for full single error correction-double error detection(SECDED) protection, Use ODD parity to generate your check bits. Output that 8-bit codeword. We ran the SEC part of the algorithm for this problem in lecture (except that was EVEN parity). You want to use procedural (always@) form for this problem. First, seed the codeword with your input data bit values. Then, calculate the values of the check bits in-situ in the codeword.

Explanation / Answer

// calculator synd:

assign synd[0] = c[0] ^ d[6] ^ d[4] ^ d[3] ^ d[1] ^ d[0];

assign synd[1] = c[1] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[0];

assign synd[2] = c[2] ^ d[7] ^ d[3] ^ d[2] ^ d[1];

assign synd[3] = ~(c[3] ^ d[7] ^ d[6] ^ d[5] ^ d[4]);

assign synd[4] = ~(c[4] ^ d[7] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0]);

// Decoder:

// The “flip” signals will be used to correct the data bits

// The “chkb” signals indicate a single checkbit error

// The “dbl” signals indicate a double-bit error

// The “badcode” signals indicate unused names and thus multibit errors

assign noerror = ~synd[4] & ~synd[3] & ~synd[2] & ~synd[1] & ~synd[0];

assign chkb[0] = ~synd[4] & ~synd[3] & ~synd[2] & ~synd[1] & synd[0];

assign chkb[1] = ~synd[4] & ~synd[3] & ~synd[2] & synd[1] & ~synd[0];

assign dbl[0] = ~synd[4] & ~synd[3] & ~synd[2] & synd[1] & synd[0];

assign chkb[2] = ~synd[4] & ~synd[3] & synd[2] & ~synd[1] & ~synd[0];

assign dbl[1] = ~synd[4] & ~synd[3] & synd[2] & ~synd[1] & synd[0];

assign dbl[2] = ~synd[4] & ~synd[3] & synd[2] & synd[1] & ~synd[0];

assign flip[3] = ~synd[4] & ~synd[3] & synd[2] & synd[1] & synd[0];

assign chkb[3] = ~synd[4] & synd[3] & ~synd[2] & ~synd[1] & ~synd[0];

assign dbl[3] = ~synd[4] & synd[3] & ~synd[2] & ~synd[1] & synd[0];

assign dbl[4] = ~synd[4] & synd[3] & ~synd[2] & synd[1] & ~synd[0];

assign flip[6] = ~synd[4] & synd[3] & ~synd[2] & synd[1] & synd[0];

assign dbl[5] = ~synd[4] & synd[3] & synd[2] & ~synd[1] & ~synd[0];

assign badcode[0]=~synd[4]& synd[3] & synd[2] & ~synd[1] & synd[0];

assign badcode[1]=~synd[4]& synd[3] & synd[2] & synd[1] & ~synd[0];

assign dbl[6] = ~synd[4] & synd[3] & synd[2] & synd[1] & synd[0];

assign chkb[4] = synd[4] & ~synd[3] & ~synd[2] & ~synd[1] & ~synd[0];

assign dbl[7] = synd[4] & ~synd[3] & ~synd[2] & ~synd[1] & synd[0];

assign dbl[8] = synd[4] & ~synd[3] & ~synd[2] & synd[1] & ~synd[0];

assign flip[3] = synd[4] & ~synd[3] & ~synd[2] & synd[1] & synd[0];

assign dbl[9] = synd[4] & ~synd[3] & synd[2] & ~synd[1] & ~synd[0];

assign flip[3] = synd[4] & ~synd[3] & synd[2] & ~synd[1] & synd[0];

assign flip[3] = synd[4] & ~synd[3] & synd[2] & synd[1] & ~synd[0];

assign dbl[10] = synd[4] & ~synd[3] & synd[2] & synd[1] & synd[0];

assign dbl[11] = synd[4] & synd[3] & ~synd[2] & ~synd[1] & ~synd[0];

assign flip[4] = synd[4] & synd[3] & ~synd[2] & ~synd[1] & synd[0];

assign flip[5] = synd[4] & synd[3] & ~synd[2] & synd[1] & ~synd[0];

assign dbl[12] = synd[4] & synd[3] & ~synd[2] & synd[1] & synd[0];

assign flip[7] = synd[4] & synd[3] & synd[2] & ~synd[1] & ~synd[0];

assign dbl[13] = synd[4] & synd[3] & synd[2] & ~synd[1] & synd[0];

assign dbl[14] = synd[4] & synd[3] & synd[2] & synd[1] & ~synd[0];

assign badcode[2]=synd[4] & synd[3] & synd[2] & synd[1] & synd[0];

// final results:

assign corrected_data = d ^ flip;

assign uncorrectable = (| dbl[14:0]) // even number of errors

| (| badcode[2:0]); // 3 or more (odd) errors

// that don't even LOOK like

// correctable errors

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