Write the VERILOG code to implement the following Finite State Machine. This FSM
ID: 3678821 • Letter: W
Question
Write the VERILOG code to implement the following Finite State Machine. This FSM has four states: St0, St1, St2, and St3. There are three inputs: Reset, A and B. There is only one output: Q1. A value of x for either of the inputs indicates that it is a “don’t care” for that transition.
In addition to writing the Verilog code, please also answer the following questions:
What is the minimum number of flip-flops needed to implement this FSM?
Is this a Mealy or a Moore Machine?
1. Verilog Implementation Write the VERILOG code to implement the following Finite State Machine. This FSM has four states: St0, Stl, St2, and St3. There are three inputs: Reset, A and B. There is only one output: Q1. A value of x for either of the inputs indicates that it is a "don't care" for that transition,. In addition to writing the Verilog code, please also answer the following questions: What is the minimum number of flip-flops needed to implement this FSM? Is this a Mealy or a Moore Machine? 1. 2. A=0, B=x A 0, B x St0 Q1-0 St2 QI=1 Reset Stl QI=0 St3 QI=1 A-1, B-x A-1, B=xExplanation / Answer
Verilog Code for FSM:
module seq_dect
(
input clk, data_in, reset,
output reg data_out
);
reg [2:0]state;
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
always @ (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)
state <= S1;
else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:
if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;
S4:
if (data_in)
state <= S1;
else
state <= S2;
endcase
end
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase
end
endmodule
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