1. Pipeline hazard (10 points) The execution flow in a pipelined CPU can be visu

Question

1. Pipeline hazard (10 points) The execution flow in a pipelined CPU can be visualized by drawing the pipeline execution diagram, An example is shown below: IF ID : EX' MEM ' wB ID IF add $2, $1, $3 Forwarding $ (data hazard) : EX MEM; WB; sub $4, $2, $5 IF Iw $3, 4($8)! ID! Draw the pipeline execution diagram of the following MIPS code given the conditions below addi $2,$zero,16 ; $2 = 16 lw $3, 8($2) bneq $3, $zero, L1 ; jump to L1 if $3!-0 subi $2, $2,4 subi $3, $3, 1 sw $2,16($2); mem sw $3, 8($2) [$2+16] = $2 L1: ; mem [$2+81 = $3 Assume: » Branch is resolved in the EX stage:; » Both ALU result and data fetched from memory are forwarded (register bypasses); » MIPS does implement the delayed branch (two delayed slots); » The 3rd instruction (bneq) turned out to be "taken"; and » Writes to the register file and memory occur at the rising edge of the clock What kinds of hazards are there? Show in the diagram with arrows addi $2,$Szero, 16F IDEXMEM WB

Explanation / Answer

1.IF ID EX MEM WB

IF ID ID EX MEM WB

IF IF ID ID EX MEM WB

IF ID ID EX MEM WB

IF ID ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

2.In 2nd instruction and 3rd instruction there will be a data hazard .That means represnt it with a stall .

IF ID EX MEM WB

IF ID ID EX MEM WB

IF IF stall ID EX MEM WB

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