What happens during the memory (M) phase for a lw instruction? What happens duri
ID: 3675985 • Letter: W
Question
What happens during the memory (M) phase for a lw instruction? What happens during write back (W) phase for a sw instruction? What-happens during the execute (X) phase for a bne instruction? What happens during the write back (W) phase for a beq instruction? What is the bit width of the rs input to the GPR? What happens during the execute (X) phase for an and instruction? What happens during the memory (M) phu.se for an and instruction? What happens during the register fetch and decode (D) phase for an addi instruction? What is the bit width of the instruction cache? What is the bit width of the data entering the ext block?Explanation / Answer
Answer for Question 1:
lw : A word is loaded into a register from the specified address.
Answer for Question 2:
sw: The contents of $t is stored at the specified address.
Answer for Question 3:
bne: Branches if the two registers are not equal.
Answer for Question 4:
beq: Branches if the two registers are equal
Answer for Question 5:
I am not sure about rs size. but i am thing it is 32 bits.
Answer for Question 6:
During Execution of AND instruction will perform the Bit wise and operation.
Answer for Question 7:
Bitwise ands two registers and stores the result in a register
Answer for Question 8:
addi: Adds a register and a sign-extended immediate value and stores the result in a register.
Answer for Question 9:
instruction cache width is typically 32 bits
Answer for Question 10:
ext2/3 blcok size typically 4096 bytes.
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