how can implement negative integers (-0 to -7) in this my vhdl ROM please. libra
ID: 3674995 • Letter: H
Question
how can implement negative integers (-0 to -7) in this my vhdl ROM please.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port( Clock : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
R : in std_logic;
A: out std_logic;
B: out std_logic;
C: out std_logic
);
end ROM;
--------------------------------------------------------------
architecture Behav of ROM is
type ROM_Array is array (0 to 7) of std_logic_vector(2 downto 0);
signal Address : std_logic_vector(2 downto 0);
constant Content: ROM_Array := (
0 => "001", -- Suppose ROM has
1 => "010", -- prestored value
2 => "011", -- like this table
3 => "100", --
4 => "101", --
5 => "110", --
6 => "111", --
7 => "000", --
OTHERS => "111" --
);
begin
process(Clock, Reset, R, Address)
begin
if( Reset = '1' ) then
Address <= "000";
elsif( Clock'event and Clock = '1' ) then
if Enable = '1' then
if( R = '1' ) then
Address <= Content(conv_integer(Address));
else
Address <= "000";
end if;
end if;
end if;
A<=Address(0);
B<=Address(1);
C<=Address(2);
end process;
end Behav;
-----------------------------------
Explanation / Answer
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port (
Clock : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
R : in std_logic;
A: out std_logic;
B: out std_logic;
C: out std_logic;
);
end ROM;
-----------------------------
architecture Behav of ROM is
type ROM_Array is array (0 to 7) of std_logic_vector(3 downto 0);
signal Address : std_logic_vector(2 downto 0);
constant Content: ROM_Array :=
(
0 => "001", -- Suppose ROM has
1 => "010", -- prestored value
2 => "011", -- like this table
3 => "100", --
4 => "101", --
5 => "110", --
6 => "111", --
7 => "000", --
OTHERS => "111" --
);
begin
P1: process(Clock, Reset, R, Address) --Sequentisl process
begin
if( Reset = '1' ) then
Address <= "000";
elsif( Clock'event and Clock = '1' ) then
if ( Enable = '1' ) then
if( R = '1' ) then
Address <= Content(conv_integer(Address));
else
Address <= "000";
end if;
end if;
end if;
A<=Address(0);
B<=Address(1);
C<=Address(2);
end process P1;
end architecture;
------------------------------
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