Build a Verilog module named “calculator” that takes in two signed 16-bit number

ID: 3672251 • Letter: B

Question

Build a Verilog module named “calculator” that takes in two signed 16-bit numbers named “in1” and “in2” and performs the following functions depending on the value of another 4-bit input named “opCode” (see table below). Be aware that the opCode is not signed, like the inputs A and B of project 2. The outputs of the module “calculator” must be a signed 16-bit number named “result”, and a 1-bit “overflow”. Be aware that the value of “overflow” doesn’t always get calculated the same way, it depends on the operation (see table below for more info and examples). The value of the output “overflow” will be one if an overflow occurred or the value of “result” is not completely accurate or correct; else the output “overflow” will be zero.

opCode

Operation that has to be performed

0000

Add both inputs. Be aware that the overflow detection when adding and subtracting must be different than for Project 2 because in Project 2 the inputs were unsigned, while now for Project 3 the inputs are signed.

0001

Subtract in1 – in2.

0010

Multiply in1 by five

0011

Divide in1 by ten. When dividing by ten, signal an overflow when in1 is not exactly divisible by ten. For instance, if in1=30, then result=3 and overflow=0; but if in1=35, then result=3 and overflow=1. You will need to explore the use of the percentage sign (%), which performs modulo operations (also known as “modulus operator”, https:// en.wikipedia.org/wiki/Modulo_operation ). The modulo finds the remainder of a division. If the remainder is zero then overflow=0; but if the remainder is not zero then produce overflow =1.

0100

Bitwise AND. Even though in1, in2 and result are declared as signed numbers, when applying the bitwise operations they are taken as raw bits. A bitwise operation (https://en.wikipedia.org/wiki/ Bitwise_operation ) is when the operation is applied to the individual bits. In this case, there will be an AND gate operation between the individual bits of in1 and the individual bits of in2; such that an AND logic will be applied to the first bit of in1 and the first bit of in2 and the output of that AND will be the first bit of result; an AND logic will be applied to the bit of position n of in1 and the bit of position n of in2 and the output of that AND will be the bit of position n of result; and so on. For example:

in1 = 1010110011110000

in2 = 1100101000110011 result = 1000100000110000

Bitwise AND, XOR and OR operations can’t overflow, so overflow=0 by default.

0101

Bitwise XOR. Similar to explanation above, but with an XOR (also known as exclusive OR) operation instead. Example:

in1 = 1010110011110000

in2 = 1100101000110011 result = 0110011011000011

0110

Bitwise OR. Similar to explanation above, but with an XOR operation instead. Example:

in1 = 1010110011110000

in2 = 1100101000110011 result = 1110111011110011

0111

One’s Complement in1. Perform one’s complement, by inverting bits (do not add one afterwards, because that would be two’s complement).
Complement operation can’t overflow, so overflow=0 by default. Examples:

in1='b00000000000000; opCode='b0111; expectedOverflow='b0; result='b1111111111111111;

in1='b0000000000000001; opCode='b0111; expectedOverflow='b0; result='b1111111111111110;

1000

Increment in1 by 1. Examples: if in1=3, then result =4. If in1=-3, then result =-2.

1001

Decrement in1 by 1. Examples: if in1=3, then result =2. If in1=-3, then result =-4.

opCode

Operation that has to be performed

0000

0001

Subtract in1 – in2.

0010

Multiply in1 by five

Explanation / Answer

module calculator(

input signed [15:0] in1,

input signed [15:0] in2,

input [3:0] opCode,

output reg signed [15:0] result

);

reg overflow;

always @ (opcode) begin

if (opCode == 0000) begin //adding in1 + in2

result = in1 + in2;