4. Consider a CPU that implements two parallel fetch-execute pipelines for super

Question

4.     Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming the instruction cycle below:

a one clock cycle fetch

a one clock cycle decode

a three clock cycle execute

and a 50 instruction sequence:

a)    No pipelining would require _____ clock cycles:

b)     A scalar pipeline would require ____ clock cycles:

c)     A superscalar pipeline with two parallel units would require ______ clock cycles:

          show your work

Explanation / Answer

a. As gven we have(1 fetch, 1 decode and 2 execute) if its a non pipelined processor, then that requires 4 clock cycles per instruction. So we need clock cycles = 4 x 60 = 240 Clock cycles for the instruction sequence.

b., it requires 60 x 1 = 60 clock cycles

c. it requires 60 x ¼ = 15 clock cycles

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