compare the memory efficiency of five different styles of instruction sets for t
ID: 3669762 • Letter: C
Question
compare the memory efficiency of five different styles of instruction sets for the code sequence below. The architecture styles are:
i. A zero-address machine is a stack-based machine where all operations are done using values stored on the operand stack. For this problem, you may assume that its ISA allows the following operations:
PUSH M - pushes the value stored at memory location M onto the operand stack.
POP M - pops the operand stack and stores the value into memory location M.
OP - Pops two values off the operand stack, performs the binary operation OP on the two values, and pushes the result back onto the operand stack.
Note: To compute A - B with a stack machine, the following sequence of operations is necessary: PUSH A, PUSH B, SUB. After execution of SUB, A and B would no longer be on the stack, but the value A-B would be at the top of the stack.
ii. A one-address machine uses an accumulator in order to perform computations. For this problem, you may assume that its ISA allows the following operations:
LOAD M - Loads the value stored at memory location M into the accumulator.
STORE M - Stores the value in the accumulator into memory location M.
OP M - Performs the binary operation OP on the value stored at memory location M and the value present in the accumulator. The result is stored into the accumulator (ACCUM = ACCUM OPM).
iii. A two-address machine takes two sources, performs an operation on these sources and stores the result back into one of the sources. For this problem, you may assume that its ISA allows the following operation:
OP M1, M2 - Performs a binary operation OP on the values stored at memory locations M1 and M2 and stores the result back into memory location M1 (M1 = M1 OP M2).
iv. A three-address machine, in general takes two sources, performs an operation and stores the result back into a destination different from either of the sources.
Consider A three-address memory-memory machine whose sources and destination are memory locations. For this problem, you may assume that its ISA allows the following operation: OP M3, M1, M2 - Performs a binary operation OP on the values stored at memory locations M1 and M2 and stores the result back into memory location M3 (M3 = M1 OP M2).
A three-address load-store machine whose sources and destination are registers. Values are loaded into registers using memory operations (The MIPS is an example of a three-address load-store machine). For this problem, you may assume that its ISA allows the following operations:
OP R3, R1, R2 - Performs a binary operation OP on the values stored at registers R1 and R2 and stores the result back into register R3 (R3 = R1 OP R2).
LD R1, M - Loads the value at memory location M into register R1. ST R2, M - Stores the value in register R2 into memory location M.
To measure memory efficiency, make the following assumptions about all five instruction sets:
The opcode is always 1 byte (8 bits).
All register operands are 1 byte (8 bits).
All memory addresses are 2 bytes (16 bits).
All data operands are 4 bytes (32 bits).
All instructions are an integral number of bytes in length. There are no other optimizations to reduce memory traffic, and the variables A, B, C, and D are initially in memory.
a. Write the code sequences for the following high-level language fragment for each of the five architecture styles. Be sure to store the contents of A, B, and D back into memory, but do not modify any other values in memory. A = B + C; B = A + C; D = A - B;
b. Calculate the instruction bytes fetched and the memory-data bytes transferred (read or written) for each of the five architecture styles.
c. Which architecture is most efficient as measured by code size?
d. Which architecture is most efficient as measured by total memory bandwidth required (code+data)?
Explanation / Answer
Write the code sequences for the following high-level language fragment for each of the five architecture styles. Be sure to store the contents of A, B, and D back into memory, but do not modify any other values in memory. A = B + C; B = A + C; D = A - B;
1.code for Stackbased Architecture
push B
push C
op
pop A
push A
push C
op
pop B
push A
push B
op
pop D
2. Code for one-address machine:
LOAD B
OP C
STORE A
LOAD A
OP C
STORE B
LOAD A
OP B
LOAD D
3.Code for a two-address machine
OP B,C
STORE A,B
OP A,C
STORE B,A
OP A,B
STORE D,A
4.CODE for A three-address machine:
OP A,B,C
OP B,A,C
OP D,A,B
5. CODE for three-address load-store machine whose sources and destination are registers.
LOAD R1,B
LOAD R2,C
OP R3,R1,R2
ST R3,A
OP R1,R3,R2
ST R1,B
OP R2,R3,R1
ST R3,D
b. Calculate the instruction bytes fetched and the memory-data bytes transferred (read or written) for each of the five architecture styles.
1. IN stack based architecutures 12 instruction bytes are fetched
memory-data bytes are 9*2=18 bytes.
2.one-address machine: instruction bytes:9
memory-data 9*2=18 bytes
3. in two address machine :instructionbytes :6
memory -data 12*2=24
4. in three address machine :instruction bytes=3
memory to data :9*2=18
5. In three-address load-store machine whose sources and destination are registers.
instruction bytes:8
memory to data :14 bytes
3.Which architecture is most efficient as measured by code size?
Three address architecture is most efficient in terms of code size
4.Which architecture is most efficient as measured by total memory bandwidth required (code+data)?
Three address load store architecutre is most efficient.
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