Write a module firstOne.sv, which accepts a 16 bit string and returns a 16 bits

Question

Write a module firstOne.sv, which accepts a 16 bit string and returns a 16 bits string that is one-hot. The output “B” should indicate the position of the “leftmost-one” in the input. For example, 11111011 10000000 ; 00001011 00001000. Note that we consider the MSB to be the left most position. Any additional modules should be included in the file. You should not change the interface provided below. (Hint: Start by thinking about our ripple carry adder, which evaluates an individual bit slice. Each slice in this case needs to know if anyone to the left has been one. Think about building a local version. Alternatively, you might be interested in using don’t care conditions in a priority case statement).

Starting point:

module firstOne (

input logic signed A[ 1 5 : 0 ] ,

output logic signed B[ 1 5 : 0 ] ) ;

// Your code here

endmodule

Any help is appreciated. The hint is really not helping me. All i can think of is to put the numbers into an array, and then use SystemVerilog functions such as (S)$left to check for a 1, shift right if not, and repeat.

Explanation / Answer

module firstOne (

input logic signed A[ 1 5 : 0 ] ,

output logic signed B[ 1 5 : 0 ] ) ;

assign adder_b=b ^ {16{sub}};

endmodule

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