A Finite State machine has the following delay value State Flip-Flops propagatio

Question

A Finite State machine has the following delay value State Flip-Flops propagation delay (from Clock Edge to Q output) (Tff): 5ns Next-State Decoder combinational logic propagation delay (Td): 10ns Outputs Decoder Combinational logic propagation delay (Tout): 15 ns State Flip-Flops Data input (D input) Setup Time (Tsu) : 3ns State Flip-Flops Data input (D input) Hold Time (Thld): 2ns Due to these delays the machine might not operate correctly when the LCock signal is too fast What is the shortest period of Clock signal for the FSM to operate correctly ___ns Maximum frequency at which the FSM can operate correctly _____MHz Show computations:

Explanation / Answer

what is the shortest period of clock signal for the FSM operate correctly?
Solution:

tCLK >= Td + Tsu
tCLK >= 10 + 3
tCLK >= 13 ns

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maximum frequency at which the FSM can operate correctly?
Solution:
f<=1/tCLK
f<=1/13
f<=0.077

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