A Digital System can be conceptually and physically subdivided into two parts or

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A Digital System can be conceptually and physically subdivided into two parts or sections: Registers and Flip-Flops Data path section and ALU section Data path section and Control Section Tri-state buffers and Registers The Stage within the FPGA-based development process where the design in defined in terms of gates, and it is verified if the design can fit into FPGA is: Simulation Logic Synthesis Post Synthesis Simulation Mapping to I/O pins Placement and Routing Select those statements that are true about the VHDL language "PROCESS" construct: Allows to specify the complex functional dependence behavior of signals Is the only scope where variables can be declared and utilized When there are not wait statements in the Process, the simulation time does not advance within the process Process blocks can be triggered concurrently no matter their ordering in the Architecture All Concurrent" statements within the process are executed in order and create future events for their output signals but are no longer sensitive to their input signals. For a positive edge-triggered Flip-Flop's the Tsu (or setup time) is: The time it takes for the Q output to go from low to high level The time the input data signal should be stable before the clock rises The time the input data signal should be stable after the clock rises The minimum input data signal duration The time it takes for the /Q output to go from high to low level Which of the following conditions can cause a D-type Flip-Flop to fail switch and instead of going into a meta-stable condition (Mark all that apply.) When the data changes less than Tsu before the clock edge When the data changes less than Tsu after the clock edge When the data changes less than Thold before the clock edge When the data changes less than Thold after the clock edge All of the above Which of the following is/are true when a FF goes into a meta-stable condition: The FF must be reset to bring it out of the metastable condition The actual Q-output level although not high nor low is at an indeterminate level. The Duration of the metasbale condition is indeterminate The Final stable (high/low) value to which Q-output resolves is indeterminate. All of the Above For an FSM the maximum clock rate (minimum clock period) depends on which factors: The time for a State FFs to change into a new Present State after the clock edge The time for Present State propagate through the Next State decoder The State FFs set-up time The State FFs hold time Alternatives a,b,c

Explanation / Answer

1.
answer-Data path section and control section(c)

2.
answer-Mapping to i/o pin (D)

3.
answer-Allow to specify the complex functional dependence behavior of signals(A)

4.
answer- The time the input data signal should be stable before the clock rises(B)

5.
answer- All of the above(E)

6.
answer-The FF must be reset to bring it out of the metastases condition(A)

7.

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