a.) What must be changed to in the pipelined datapath to add this instruction to
ID: 3631910 • Letter: A
Question
a.) What must be changed to in the pipelined datapath to add this instruction to the MIPS ISA?
b.) Which new control signals must be added to your pipeline from a?
c.) Does support for this instruction introduce any new hazards? Are stalls due to exsiting hazards made worse?
d.) Give an example of where this instruction might be useful and a sequence of exsisting MIPS instruction that are replaced by this instruction.
Please help! I am really confused by the pipeline concept
a.) What must be changed to in the pipelined datapath to add this instruction to the MIPS ISA? b.) Which new control signals must be added to your pipeline from a? c.) Does support for this instruction introduce any new hazards? Are stalls due to exsiting hazards made worse? d.) Give an example of where this instruction might be useful and a sequence of exsisting MIPS instruction that are replaced by this instruction. Please help! I am really confused by the pipeline conceptExplanation / Answer
Dear, Able to help you you with a,b,d parts only. a) a. This instruction behaves like a load with a zero offset until it fetches the value from memory. The pre-ALU Mux must have another input now (zero) to allow this. After the value is read from memory in the MEM stage, it must be compared against zero. This must either be done quickly in the WB stage, or we must add another stage between MEM and WB. The result of this zerocomparison must then be used to control the branch Mux, delaying the selection signal for the branch Mux until the WB stage. b. We need to compute the memory address using two register values, so the address computation for SWI is the same as the value computation for the ADD instruction. However, now we need to read a third register value, so Registers must be extended to support a another read register input and another read data output and a Mux must be added in EX to select the Data Memory’s write data input between this value and the value for the normal SW instruction. b) a. We need to add one more bit to the control signal for the pre-ALU Mux. We also need a controlsignal similar to the existing “Branch” signal to control whether or not the new zero-compare
result is allowed to change the PC. b.We need a control signal to control the new Mux in the EX stage. d) a. Eg. BEZI can be used when trying to fi nd the length of a zero-terminated array lw Rtmp,0(Rs)
beq Rt,$0,Label b. E.g., SWI can be used to store to an array element, where the array begins at address Rt and Rs is used as an
index into the array. add Rtmp,Rs,Rt
sw Rd,0(Rtmp) Hope this will help you..
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