True or False: (80 points) 1. Static RAM is a faster and more dense memory than

Question

True or False: (80 points)
1. Static RAM is a faster and more dense memory than DRAM
Ans-:.
2. ROMs cannot be used even when only few bits are corrupted.
3. Hamming code is a typical error correcting mechanism used to repair Hard failures.
4. Read-mostly memory is a type of random-access memory.
5. Hard failures in the memory cannot be repaired and hence have be replaced or spares have to be
added.
6. ROM can be used to store frequently accessed functions.
7. The memory devices used in a computer form a hierarchy based on a set of characteristics.
8. The lowest level of memory in the hierarchy is the closest to the processor.
9. The size of a word is typically equal to the number of bits required to represent an integer.
10. Semiconductor ROM memory is a nonerasable but volatile type of memory.
11. Direct mapping implies that the number of lines in the cache must be equal to the main memory.
12. The best among the three cache replacement algorithms is the least recently used (LRU) algorithm.
13. The write back policy allows the new data to be written both in the cache and the main memory.
14. The program counter stores the address of the next instruction to be executed.
15. Multiple interrupts cannot be handled by the processor.
16. The program counter stores the address of the next instruction to be executed.
17. The fundamental building block of the ENIAC machine was transistors.
18. The stored program concept is used in both ENIAC and Von-Neumann machines.
19. The Intelx86 architecture is CISC-based.
20. Intel has not produced chips with architecture that run 64-bit instructions.

Multiple Choice: (120 points)
1. What number system was used in the ENIAC machine?
A. Binary B. Decimal
C. Octal D. Hexadecimal

2. The Memory Address register stores the address of the word stored in which part of the architecture?
A. I/O B. Program Counter
C. Memory Buffer Register D. None of the above

3. The five important parts of the Von Neumann Machine are:
A. Fetch Unit, ALU, Memory, Registers and I/O
B. Central Arithmetic, Central Control, Memory, Registers and I/O
C. Fetch Unit, Decode, ALU, Memory and I/O
D. Central Arithmetic, Fetch Unit, Control, Registers and Buses.

4. What is the second generation computers made?
A. Vacuum tubes B. Integrated Circuits
C. Resistors D. Transistors

5. What are the fundamental blocks of the third generation computers and what were they made of?
A. Integrated Circuits consisting of capacitors
B. Digital Circuits using vacuum tubes
C. Integrated Circuits made using transistors
D. None of the above

6. What did Moore’s law predict about the density and size of future generation chips?
A. Density decreases and size doubles
B. Density increases drastically and size reduces
C. Density increases but size remains the same
D. No impact on size and density

7. What technology was used to create memories?
A. Vacuum tube based technology
B. Same integrated circuit technology as the processors
C. Capacitor based network technology
D. Inductive circuitry

8. What changes can be done to the I/O buses to speed up the transfer of data between the processor and memory
A. Increase bus width B. Decrease the frequency of transfer
C. Add buffers for the I/O D. All of the above

9. The performance of a processor can be measured using
A. Clock period B. Cycles per Instruction
C. Throughput D. All of the above

10. How are data and instructions stored in the Von Neumann architecture?
A. In separate memories B. Dual ported memory
C. Unified read-write memory D. None of the above

11. What are the parts of an instruction cycle?
A. Fetch and Execute Cycle B. Fetch, decode and execute cycles
C. Decode and Store cycle D. Fetch, decode, execute and store.

12. Where is the fetched instruction stored?
A. Instruction register B. Program Counter
C. Instruction buffer register D. None of the above

13. Which of the following is a type of interrupt?
A. I/O interrupt B. Program Interrupt
C. Hardware/power failure D. All of the above

14. What are the interconnection wires not in the bus structure?
A. Data lines B. Instruction lines
C. Address lines D. Control lines

15. To which of the following buses is the memory connected to?
A. High-performance bus B. Control bus
C. System Bus D. Interface bus

16. The local bus connects which two components of the system?
A. Memory and I/O module B. Processor and cache
C. Cache and Register bank D. None of the above

17. The CPU system bus involves transfer of
A. Control B. Data
C. All of the above D. Instruction

18. Early microprocessors had an instruction cycle consisting of these stages
A. Fetch, Decode and Execute B. Fetch, Execute, Interrupt
C. Fetch, Decode, Write Back D. All of the above

19. The control unit must keep in its control, the stage of
A. Registers B. Resources
C. All of the above D. Instruction cycle
20. Control unit has a direct access to this register
A. Architectural registers B. Symbolic registers
C. Instruction register D. None of the above

21. How are data stored in the internal memory?
A. Bytes B. Words
C. Pages D. A or B

22. Which of the following memory types is visible to the user?
A. Main memory B. Virtual Memory
C. Level 3 cache D. None of the above

23. Which of the following is not included in each line of the cache
A. Tag B. Valid bit
C. Flag D. Dirty bit

24. Memory address in set-associative cache is interpreted into the three fields namely;
A. tag, set and word B. tag, set and byte
C. valid bits, set and byte D. valid bits, set and word

25. Random cache line replacement policy performs close to which other policy
A. LRU B. LFU
C. FIFO D. All of the above

26. From the following, which type of memory is not a read-mostly memory?
A. EEPROM B. PROM
C. Flash D. EPROM

27. Which among the following is not as method of accessing data?
A. Sequential B. Asynchronous
C. Random D. None of the above

28. An important attribute of RAM memories is
A. Random access & non-volatile B. Volatile
C. Sequential access D. None of the above

29. Which of the following is a type of DRAM
A. Advanced DRAM B. DDR DRAM
C. RDR DRAM D. None of the above

30. What happens when a bit of data is incorrect in a ROM
A. Error correction will be used B. Redundancy will help
C. ROM cannot be used D. None of the above

Explanation / Answer

Dear user, True/False: 1. False, Because Static RAM is a faster than DRAM but not more dense memory. 2. False 3.True 4.False, Because Read-mostly memory is a type of ROM(Read only memory) 5.True 6.False Because, RAM can be used to store frequently accessed functions but not ROM cann't do it. 7.True 8. False Because the upper level of memory in the hierarchy is the closest to the processor. 9.True 10.True 11. True 12.False Because, the best among the three cache replacement algorithms is the Most Recently Used(MRU) algorithm. 13.True 14.True 15. Fasle Because, multiple interrupts can be handled by the processor. 16. True 17. True 18. False 19. True 20. False Because, Intel has produced chips with architecture that run 64-bit instructions. Note: Please another post for remaining bits.

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