Below is an active high S-R latch and below it is the timing diagram showing the

Question

Below is an active high S-R latch and below it is the timing diagram showing the state of the lat at each clock cycle. Explain for each of the states why the output (ieQ) is so?

Explanation for each of the states of the S-R Latch for the 10 clock cycles.

Column 1: initial condition S=0 , R=0 and Q=1 (a set condition)

Column 2: S=1 (set the latch) R stays 1 and Q stays 1..nothing

Column 3: S=0 again nothing happened it is already set

Column 4: R=1 (reset the latch) Q=0 ..so it is reset

Column 5: R=0 nothing happened as it is already reset

Column 6: R=1 (reset command)

Column 7,8,9…stays in a reset condition until a

Column 10: set comes again like column 4

Explanation / Answer

Soln :::::

From the timing diagram , your S-R latch Seems likes an Asynchronous Cross -coupled NOR gates active High Inputs ....

===)Column 1: initial condition S=0 , R=0 and Q=1 (a set condition)
S-R NOR Latch have Storage Conditions when Both Set-Reset port are at '0s' . While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q.

====)Column 2: S=1 (set the latch) R stays 1 and Q stays 1..nothing
When Set is equals to the logic '1' , & Reset stays at '0' , then S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high .

===)Column 3: S=0 again nothing happened it is already set

If again it is SET (S) to '0' , as stated above , If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low . Beacuse it is STORAGE CONDITION OF S-R NOR LATCH.

====) Column 4: R=1 (reset the latch) Q=0 ..so it is reset

Now Reset is put at logic '1' , In this case previously Q has its logic high '1' , after feding R to logic high , Q gone to Logic Low ,due Both Logic High in to nOR gates..

===)Column 5: R=0 nothing happened as it is already reset
Again R is given to Logic LOW and SET(S) is at also LOW , SInce this the Storage Condtions of the S-R NOR latch due to While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state

====)Column 6: R=1 (reset command)

After Reset is Given to LOGIC LOW , After the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state ,if R is pulsed high while S is held low, then the Q output is forced low .

====)Column 7,8,9…stays in a reset condition until a

Column Have the Storage Cndition as Q='0' as in Coulmn 6 , in Coulmn 8 , Reset is again at the Logic High So In NOR gate , the two INPUT previous Q'=1 & RESET HIGH '1' at NOR comes in to force Q to Logic ZERO .

In Coulmn 9 , Again Storage Condition ,So Q stays at LOW .

====)Column 10: set comes again like column 4

Both SET & RESET is at Logic HIGH , this is the INDETEERMINATE STAGE ...it can be any thing ..May be Logic HIGH or Logic LOW ..

Thanking You ...

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