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The instruction: lw $12, flag could be synthesized from three TAL instructions:

ID: 3621738 • Letter: T

Question

The instruction:

lw $12, flag

could be synthesized from three TAL instructions:

lui $12, high_address
ori $12, $12, low_address
lw $12, ($12)

However, by recognizing that the lw instruction can have a 16-bit offset, the latter two instructions can be combined into a single instruction, for example, with..

lui $12, high_address
lw $12, low_address($12)

This sequence works correctly only if the most significant bit of 16-bit representation of low_address is zero. If it is one, a similar sequence can be constructed, but an adjustment must be made. What is the adjustment?
Need help! Thanks in advance.

Explanation / Answer

Dear, lw $12, flag becomes la $12, flag lw $12, 0($12) which becomes lui $12, high_address # label represents an address ori $12, $12, low_address lw $12, ($12) or lui $12, high_address lw $12, low_address($12) Note that this 2-instruction sequence only works if the most significant bit of the low_address of label is a 0. The la instruction is also a pseudoinstruction (MAL, but not TAL). Its synthesis is accomplished with the 2 instruction sequence of lui followed by ori as given above. The lui instruction places the most significant 16 bits of the desired address into a register, and the ori sets the least significant 16 bits of the register. Trap should occur due to something in instruction stream if we set the bit low_address. It arrives synchronously (while instruction is executing). A good test: if program was re-run (with the same input), the trap would occur in precisely the same place in the code. examples: o unaligned address error So, if a user's application had the code: o lw $12, 1($sp) this would most probably cause a trap. The value of 1 + $sp is not likely to be a multiple of 4. For a lw instruction, the address calculated must be a multiple of 4. o arithmetic overflow o syscall o divide by zero lw $12, 4($12) it is the adjustment

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