Recall that we have two write policies and write allocation policies, their comb
ID: 3613125 • Letter: R
Question
Recall that we have two write policies and write allocation policies, their combinations can be implemented at either in L1 or L2 cache. Buffers are employed between different levels of hierarchy to reduce access latency. For this given configuration, list the buffers needed between L1 and L2 caches,as well as L2 cache and memory. Describe the procedure of handling an 1.1 write miss, sidering the component involved and the possibility of replacing a dirty block. For a multilevel exclusive cache (a block can only reside one of the 1.1 and 1.2 caches) configuration, describe the procedure of handling L1 write miss,considering the component involved and the possibility of a dirty block. Consider the following program and cache behaviors. For a write-through, write-allocate cache, what's the minimum read and write bandwidths (measured by byte-per-cycle) needed to achieve a CPI of 2? For a write-back, write-allocate cache, assuming 30% replaced data cache blocks are dirty, what's the minimal read and write bandwidth needed for a CPI of 2? What are the minimal bandwidths needed to achieve performance of CPI = 1.5?Explanation / Answer
please rate - thanks 5.5.1 a. L1 => Write-back buffer => L2 => Write buffer b. L1 => Write-back buffer => L2 => Write buffer 5.5.2 a. 1. Allocate cache block for the missing data, select areplacement victim; 2. If victim dirty, put it into the write-back buffer, which willbe further forwarded into L2 write buffer; 3. Issue write miss request to the L2 cache; 4. If hit in L2, source data into L1 cache; if miss, send writerequest to memory; 5. Data arrives and is installed in L1 cache; 6. Processor resumes execution and hits in L1 cache, set the dirtybit. b. 1. If L1 miss, allocate cache block for the missing data, selecta replacement victim; 2. If victim dirty, put it into the write-back buffer, which willbe further forwarded into L2 write buffer; 3. Issue write miss request to the L2 cache; 4. If hit in L2, source data into L1 cache, goto (8); 5. If miss, send write request to memory; 6. Data arrives and is installed in L2 cache; 7. Data arrives and is installed in L1 cache; 8. Processor resumes execution and hits in L1 cache, set the dirtybit. 5.5.3 a. Similar to 5.5.2, except that (2) If victim clean, put it into avictim buffer between the L1 and L2 caches; If victim dirty, put it into the write-back buffer,which will be further forwarded into L2 write buffer; (4) If hit in L2, source data into L1 cache,invalidate the L2 copy; b. Similar to 5.5.2, except that – if L1 victim clean, put it into a victim buffer between theL1 and L2 caches; – if L1 victim dirty, put it into the write-back buffer,which will be further forwarded into L2 write buffer; – if hit in L2, source data into L1 cache, invalidate copy inL2; 5.5.4 a. 0.166 reads and 0.160 writes per instruction (0.5 cycles).Minimal read/write bandwidths are 0.664 and 0.640 byte-per-cycle. b. 0.152 reads and 0.120 writes per instruction (0.5 cycles).Minimal read/write bandwidths are 0.608 and 0.480 byte-per-cycle. 5.5.5 a. 0.092 reads and 0.0216 writes per instruction (0.5 cycles).Minimal read/write bandwidths are 0.368 and 0.0864 byte-per-cycle. b. 0.084 reads and 0.0162 writes per instruction (0.5 cycles).Minimal read/write bandwidths are 0.336 and 0.0648 byte-per-cycle. 5.5.6 a. Write-back, write-allocate cache saves bandwidth. Minimalread/write bandwidths are 0.4907 and 0.1152 byte-per-cycle. b. Write-back, write-allocate cache saves bandwidth. Minimalread/write bandwidths are 0.4478 and 0.0863 byte-per-cycle
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.