4. What is the bandwidth of a memory system that transfers 32 bits of data per r

Question

4. What is the bandwidth of a memory system that transfers 32 bits of data per request, has a latency of 30 ns per operation, and has a precharge time of 5 ns between operations? 5. Suppose a DRAM has a RAS-CAS delay of 40 ns, has a CAS-data delay of 25 ns, and requires a precharge time of 10 ns. If the DRAM does not support page mode and returns 4 bits of data from each memory reference, what is its latency for read operations, throughput (assume reads and writes take the same amount of time), and bandwidth? IF a DRAM has a 256 rows, and its refresh time is 10 ms, how often (on average) does a row refresh operation need to be done? 6. 7. What are the hit and miss rates in the cache and the main memory if the processor executes a total of 1,500,000 memory references, ,1200,000 of which hit in the cache and 300,000 of which hit in the main memory.

Explanation / Answer

4)

= 4 bytes / 35 ns

= 4 bytes / 35 * 10-9 ns

= 0.11 * 109 bytes/s

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6) Given DRAM has 256 rows , refresh time is 10 ms. We know the following formula

Refresh Time Interval = Refresh Time / Number of Rows

= 10 ms / 256

= 0.039 ms

= 0.039 * 10-3 seconds

Hence, refresh operation can be done for every  0.039 * 10-3 seconds.

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7) Given Total memory references = 1,500,000.

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5) Total time to read the DRAM = RAS-CAS delay + CAS- data delay = 40 ns + 25 ns = 65 ns

Hence Latency for read operation = 65 ns

Given percharge time is 10 ns

Hence one memery reference can initiate every (65+10)ns = 75 ns.

Each memory reference fetches 4 bits of data.

herefore, bandwidth of the system is = 4 bits / 75 ns = 0.053 * 109 bits/second

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