lesign produces one additional outpu and O otherwise. This allows the user to kn

Question

lesign produces one additional outpu and O otherwise. This allows the user to know when the lock is in the Wait state, and also enables the the wait state is correctly entered. ake implementation easier, the transition from Red2 to Wait is changed from the textbook: add the cor sed) on this transition. In addition, add an arrow from Red2 back to Red2 on the condition a' (no buttor ges, the door will stay unlocked after the correct code is entered until another button is pressed. t, w, not included in the textbook description. This output should Inputs: s,r,g,b,a Outputs: u, W Wait u=0 W:=1 r. Start a w=0 u=0 arb'g Red1 u- W-0 Bluegrb u=0 Green Red2 u=0 u=1 W=0

Explanation / Answer

I have written the async verilog code for the above statement machine. the code is written as per the FSM descirbed in the code.

working verilog code as per the FSM with comments:

We have all the condition in the state machine to implement the code. We just need to implement the logic for the states as per the FSM described above.

We have s,r,g,b and a are inputs to this FSM.

assign next_state[1]= (state[0] & s) | (state[1] & ~a);

// logic for this code is that we need to detemine the condition when we will reach state 2 which is red1. Now it can be reached in 2 coniditions.

// 1) where we are in state1 and want to go to state2. the first condition in verilog statement.

// 2) when we are in state 2 itself.second condition in verilog.

assign next_state[2] = (state[1] & a & r & ~b & ~g) | (state[2] & ~a);

// logic for this code is that we need to detemine the condition when we will reach state 3 which is blue. Now it can be reached in 2 coniditions.

// 1) where we are in state2 and want to go to state3. the first condition in verilog statement.

// 2) when we are in state 3 itself.second condition in verilog.

assign next_state[3] = (state[2] & a & b & ~r & ~g) | (state[3] & ~a);

// Similary we have other logic in FSM

assign next_state[4] = (state[3] & a & g & ~r & ~b) | (state[4] & ~a);

assign next_state[5] = (state[4] & a & r & ~b & ~g) | (state[5] & ~a);

//now u = 1 only when state is red2 or 5

assign u = state[5];

//w=1 onlt when state is wait or 0.
assign w = state[0];

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