compleate this code using this binary number 0001 0011 0101 0101 -- fsm2.vhd ---
ID: 3595824 • Letter: C
Question
compleate this code using this binary number
0001 0011 0101 0101
-- fsm2.vhd
-----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
entity FSM2 is
port( X: in std_logic;
R,CLK: in std_logic;
Z: out std_logic);
end;
-----------------------------------------------------
architecture FSM2_ARCH of FSM2 is
-- modify this line to include the appropriate number of states
type state_type is (S0,S1,S2,...);
signal NS, CS: state_type;
begin
STATE_CONTROL: process(CLK,R)
begin
if CLK'event and CLK='1' then
if R='1' then
CS <= S0;
else
CS <= NS;
end if;
end if;
end process;
-- modify for the last four of your user ID
-- e.g.: last four UID = "6633" => "0110011000110011" LSB goes in first ...
COMB_LOGIC: process(CS,X)
begin
case CS is
when S0 => -- detected nothing
Z <= '0';
if X='0' then
NS <= S0;
elsif X='1' then
NS <= S1;
end if;
when S1 => -- detected '1'
Z <= '0';
if X='0' then
NS <= S0;
elsif X='1' then
NS <= S2;
end if;
when S2 => -- detected "11"
Z <= '0';
if X='0' then
NS <= S3;
elsif X='1' then
NS <= S2;
end if;
when S3 => -- detected "110"
Z <= '0';
if X='0' then
NS <= S4;
elsif X='1' then
NS <= S1;
end if;
when S4 => -- detected "1100"
Z <= '0';
if X='0' then
NS <= ??;
elsif X='1' then
NS <= ??;
end if;
when S5 =>
when S6 =>
.
.
.
end case;
end process;
end;
Explanation / Answer
we know that the full adder sum = A xor B xor Cin and Cout = AB+BCin+ACin
by using these sum and carry we can write Full Adder VHDL Code as Shown below.
###############################################################################
VHDL Code for Full Adder :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity Full_Adder is
Port ( A : in STD_LOGIC; --A Input port
B : in STD_LOGIC; --B Input port
Cin : in STD_LOGIC; --Cin Input port
Sum : out STD_LOGIC; --Sum output port
Co : out STD_LOGIC); --Co is Carry out out put port
end Full_Adder;
architecture FOR_CLASS of Full_Adder is
begin
process(A,B,Cin)
begin
for i in 0 to 7 loop
Sum(i) <= A(i) xor B(i) xor Cin(i);
Co(i) <= ((A(i) and B(i)) or (B(i) and Cin(i)) or (A(i) and Cin(i)));
end for;
end process;
end FOR_CLASS;
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