4. [10 pts, 5 pts for each part of the analysis (tsetup and thold constraint) Su

Question

4. [10 pts, 5 pts for each part of the analysis (tsetup and thold constraint) Suppose you add registers to the 16-bit prefix adder from the book, as indicated by the blue rectangles in the figure below: you have a register producing the values Ai-1:0, Bi-1:0, and Cin (i.e., C-1) at time t-0 and a second register sampling the result of the sum after the calculation is complete. What is the fastest frequency at which you can run the prefix adder? The two- input gate delays are tpd-150ps, tod-100ps. The registers have the following timing characteristics: tpcq200 ps, tccq-120 ps, thold-75 ps, and tsetup-110ps. Remember to examine both setup and hold time constraints. 15 14 1312 11 10 987 6 5 4 3 2 01 14:13 10:9 8:7 6:5 4:3 0:-1 10:7 9:7 6:35:3 14:7 13:7 12:711:7 6:-1 5:-1 4-1 3:-1 14-1 13-1 12-1 11:-1 10:-1 9:-1 | 8:-1 | 7:-1 15 14 1312 11 10 987 65 4 3 2 0 Legend A, B G-1 1A, B Pi Gii Pti Gi i:j i:j

Explanation / Answer

consider the 16 bit prefix adders, (blue rectangles), middle circuit in the below.

first step is to calculate, the delay in the longest path.

delay 1 = tpd of AND gate + tpd of OR gate = 200ps + 200ps= 400 ps

now consider the clk timing of register (flip flop):

delay 2 = FF ack time+ setup time+ hold time = 120ps+75ps + 110ps = 305 ps

total delay = 400+305 = 705 ps

fastest frequency = 1/ total delay = 1/705ps = 1418439716.31 Hz = 1418.439 MHz

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