SUBJECT: Computer Architecture PROBLEM: What is the Multicycle Instruction Datap
ID: 3591345 • Letter: S
Question
SUBJECT: Computer Architecture
PROBLEM: What is the Multicycle Instruction Datapath for the instruction type addi $15, $20, 5?
The explanation should just address the 2nd cycle and subquestions below:
(2) Instruction Decode and Register Fetch
(a) What values are read which the registers, and what happens to those values?
(b) What else occurs durring this step (i.e. what does the ALU do)? You have the wrong value listed for operand 1, and you have two different values being listed as operand 2 -- which is used?
(c) What control signals cause all this to happen?
Explanation / Answer
As with the single-cycle implementation our processor will consist of two cooperating units the datapath and the control. We will first design the datapath and then the control. The key difference here is that the execution of a single instruction will take multiple cycles to complete. Accordingly, the datapath will have to change a bit.
The high-level methodology used to develop this datapath is the following: We approach instruction execution as a sequence of small steps/actions. Instead of trying to perform all these actions in one giant step/cycle we instead partition them into groups that are performed in order one after the other. Roughly the groups we will use here are:
1. Read instruction from memory.
2. Decode instruction and speculatively read two registers that the instruction might use
3. Perform ALU calculations or access memory.
4. Write result back to register file.
5. Determine next PC and update PC.
Because these steps will be executed in separate cycles it is necessary to introduce additional storage elements to remember what step of the execution we are at and to hold information as long as it might needed.
The figure that follows shows the datapath. You will notice that it is slightly different than the single cycle datapath. One key difference is the introduction of temporary registers to hold the outcomes that are produced at each cycle. For the time being please ignore the details and focus on the grey boxes. These are the new registers but keep in mind that these registers are not visible to the programmer:
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