The MIPS ISA defines two versions of the add instruction which differ as to how

Question

The MIPS ISA defines two versions of the add instruction which differ as to how they handle overflow e.g. add traps (which usually results in throwing an exception) if the addition results in two's-complement overflow, but addu simply ignores the overflow. However, the ISA does not define an instruction that traps if there is unsigned overflow. If a program works with unsigned numbers, and detecting overflow is important, then the program must test the result of each addition operation to see if overflow has occurred. One way to do this is as follows: When adding unsigned numbers, the result will never be less than either operand. If overflow occurs, it will always be less than both of the operands. Example: Oxffff0000 + 0x10000000-0x0fff0000 because of overflow. Moreover, the result is less than both of the Write an assembly-language program fragment which adds the unsigned values in $4 and $5, putting the result in $6, with trapping if overflow occurs. (The following instruction can be used to force the appropriate trap to occur: break 0x6). (Hint: you will need to use a temporary register for slt. Use $1.)

Explanation / Answer

addu $6,$4,$5
addi $t0,$zero,1   
slt $1,$6,$4
beq $1,$t0,exit
slt $1,$6,$5
beq $1,$t0,exit
j end
exit : break 0x6
end :

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