maximum rite a VHDL subprogram that implements the function of finding the of 4
ID: 3585006 • Letter: M
Question
maximum rite a VHDL subprogram that implements the function of finding the of 4 inputs. The subprogram should take four 8-bit unsigned std_logic_vectors as inputs and output an integer result. The result should be the index (0-3) of the input that was the maximum of the four input std_logic_vectors. Note: if you have multiple inputs having the same maximum value, take the first on index, eg, for inputs "34, 51, 255, 255”, (expressed as integers) take the third input as the ma l) W e for the output 2) Write a VHDL subprogram that implements the function of finding the minimum of 4 inputs. The subprogram should take four 8-bit unsigned std_logic_vectors as inputs and output an integer result that is the index (0-3) of the input that was the minimum of the four input std_logic_vectors. Note: if you have multiple inputs having the same minimum value, take the first one for the output index. Write a VHDL entity and architecture that implements a comparator that finds out the maximum number and minimum number in 4 8-bit inputs. Your comparator is required to output the values of the max and min PLUS their indexes. For example, for 4 inputs "34, 51, 0, 255", (expressed as integers) your comparator determines that the fourth input is the max and its value is 255; the third input is the min and its value is 0 Your comparator should have the following ports ports) type ino- in3 8-bit std logic vector inputs 8-bit inputs to be compared max index 2-bit std_logic_vector output Index (0-3) of input with max value min index 2-bit std logic vector output Index (0-3) of input with min value max value 8-bit std logic vector output Value of max input min value 8-bit std_logic vector output Value of min input meaning For the example inputs "34, 51, 0, 255", i.e., ("0010_0010", "0011_0011", 0000_0000", "1111 1111"), your comparator should have the following outputs: max_index 11; min_index: 10; max_value 1111_1111; min_value: 0000_0000;Explanation / Answer
1.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity maximum_four is
Port ( NO_IN : in STD_LOGIC_VECTOR (7 downto 0); -- Input stream
ENA : in STD_LOGIC; -- Enable
CLK : in STD_LOGIC; -- Clock
MAX_OUT : out STD_LOGIC_VECTOR (7 downto 0));-- The maximum of the stream
end maximum_four;
architecture Behavioral of maximum_four is
signal max : std_logic_vector(7 downto 0):="00000000";
begin
comparator:
process(CLK)
begin
if (ENA='1') then
if (CLK'event and CLK ='1') then
if ( NO_IN > max ) then
max <= NO_IN;
else
max <= max;
end if;
end if;
else
min <= min;
end if;
end process;
MAX_OUT <= max;
end Behavioral;
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