The following diagram shows the datapath design of the ARM7 processors. Clearly

Question

The following diagram shows the datapath design of the ARM7 processors. Clearly explain the basic functions of the barrel shifter, incrementer and register bank in the above datapath design. (b) With the aid of a diagram, detail the 3-stage pipelining mechanism used in the ARM7 processors. (c) After knowing that ARM9 processors use 5-stage pipelines for program execution, a student argues that when compared to the 3-stage pipelines used in the ARM7 processors, the latency of each instruction in a program is increased from 3 clock cycles to 5 clock cycles for the ARM9 processors. Therefore, using the 5-stage pipelines will definitely degrade the overall performance of the ARM9 processors. Will you agree with the student's argument or not ? Justify your answer with clear explanations.

Explanation / Answer

ARM7 is 3-stage pipeline: IF-ID-EX
while ARM9 is 5-stage pipeline IF-ID-RF-EX-WB.

RF: register fetch, WB: write-back, EX: execute, IF: instruction fetch,
ID: instruction decode.

Also ARM9 is designed for better performance (~200MHz) where as ARM7 operates in region: 20-66MHz.

T stands for Thumb 16-bit compressed instruction set.

The ARM7/9 variants like 710, 966 etc feature stuff among: cache memories, MMU, DMA controller.

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