Suppose the following MIPS program is executed in a pipelined MIPS processor: ad
ID: 3581778 • Letter: S
Question
Suppose the following MIPS program is executed in a pipelined MIPS processor:
add $s0, $s0, $s0
lw $s1, 0($s0)
add $s1, $s1, $s1
add $s2, $s0, $s1
Which is true?
a. Operand $s0 of lw will be forwarded from the prior instruction, the add following lw will be stalled in the Decode stage for one clock cycle, the operands $s0 and $s1 of the last add will both be forwarded from prior instructions.
b. The add following lw will be stalled in the Decode stage for one clock cycle, and the operand $s0 of the last add will be forwarded from a prior instruction.
c. Operand $s0 of lw will be forwarded from the prior instruction, the add following lw will be stalled in the Decode stage for one clock cycle, and the operand $s1 of the add following lw will be forwarded from the WB stage of lw.
d. Operand $s0 of lw will be forwarded from the prior instruction, and the add following lw will be stalled in the Decode stage for two clock cycles.
Please thoroughly explain how you came to this answer.
Explanation / Answer
Answer:
Correct Answer is Option b i.e Operand $s0 of lw will be forwarded from the prior instruction, the add following lw will be stalled in the Decode stage for one clock cycle, and the operand $s1 of the add following lw will be forwarded from the WB stage of lw.
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