Really hope someone can help me with the correct procedures, I posted the questi

Question

Really hope someone can help me with the correct procedures,

I posted the question twice, and got the feedback with wrong procedures and wrong answers.

Answer Key: 0.8|0.8ns|0.8 ns, 3.2|3.2ns|3.2 ns, 312.5, 1250, 3.99, 4, 4, 1.75, 0.57

Just need the basic steps for getting these answers.

please do not provide me with imcomplete procedures that comeup with different answers, Sincerely

A CPU has a dock rate of 1.25Ghz. Let us assume that the CPU has 4 pipeline stages and processing delay of each stage is exactly one clock cycle period. What is the clock period in ns? What is the execution time (in ns) of each instruction passing through all stages? What will be the instruction throughput (instructions/sec) in MIPS with sequential (serial e.. no pipeline) execution? What will be the instruction throughput (instructionssec in MIPS with pipeline operation? What is the speed-up achieved when 500,000 instructions are processed using the pipeline operation up to two decimal places) What is the speed-up achieved when 1,000,000 instructions are processed using the pipeline operation? (round it to nearest intege What will be the maximum speed-up achieved with this pipeline? and the probability that a branch is taken is 50%, what will be the average CPI for this CPU? Given that the branch penalty is 10 cycles, the probability of a branch instruction is 15% What will the execution efficiency? (up to two decimal places)

Explanation / Answer

clock rate of 1.25 Ghz = 1.25*106 cycles in 1 second. Then 1 cycle will take 1 / (1.25*106) = 8*10-10 = 0.8*10-9 second

= 0.8 ns

Each instruction will pass through 4 pipeline stages. Each stage has delay of 1 cycle. So, total execution time = 0.8*4 = 3.2 ns

Number of instructions in non pipeline = 1 / (3.2*10-9) = 0.3125*109 = 312.5 Million instructions or 312.5 MIPS

Since the pipeline has 4 stages, the ideal speedup over non pipeline is 4 (equal to the number of pipeline stages). This is because in the steady state, 4 instructions can execute parallely in different stages. So, the instruction throughput is 312.5*4 = 1250 MIPS

for 500000 instructions,

time taken in non pipeline architecture = 3.2*5*105 = 16*105 ns

For pipeline instruction, the 1st instruction takes 3.2 ns. Remaining 499999 instructions will take 499999*0.8 = 399999.2 ns. Total time taken = 4.000024*105 ns.

Speedup = 16 / 4.000024 = 3.99 (upto 2 decimal places)

Similarly, for 1000000 instructions, time taken in non-pipeline = 32*105 ns

In pipeline, time taken = 3.2 + 999999*.8 = 8.000042*105 ns.

So, speedup = 32 / 8.000042 = 3.9999790001102494211905387496716 = 4 (rounding to nearest integer)

If the number of instructions is infinity, speedup = no of pipeline stages = 4

Probability of branch instruction = 15% and probability of branch taken = 50%.

So, out of 100 insrtuction 15 are branch instruction. Out or the 15 only 7.5 (50%) are taken.

So, per 100 instruction, branch penalty = 10*7.5 = 75 cycles.

So, 100 instructions will take 100+75 = 175 cycles instead of 100 cycles to complete. Hence, the CPI = 175 / 100 = 1.75

Out of 175 cycles, 100 are useful and the rest are wasted cycles due to branch. So, execution efficiency = 100/175 = 0.57

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