Given the following VHDL code, clearly explain what the assignment statement ins
ID: 3579724 • Letter: G
Question
Given the following VHDL code, clearly explain what the assignment statement
inside the process does.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
entity exam is
generic (N : integer := 8);
port(
load : in STD_LOGIC;
clock : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(N-1 downto 0);
q : out STD_LOGIC_VECTOR(N-1 downto 0)
);
end exam;
architecture test of exam is
signal regg : STD_LOGIC_VECTOR(N-1 downto 0);
begin
process(load, clk, data_in)
if (load = '1') then
regg <= data_in;
elsif (rising_edge(clk)) then
regg <= "00" & regg(N-1 downto 2);-- What does this do?
end if;
end process;
q <= regg;
end test;
Explanation / Answer
Explanation:
If the load is 1 then data_in values stored in the regg next to the clock is high, then regg reset to ‘00’ then starts count from 7 to 2. And finally stores the regg value in
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