The latencies of individual stages in five-stage MIPS (Microprocessor without In
ID: 3576610 • Letter: T
Question
The latencies of individual stages in five-stage MIPS (Microprocessor without Interlocked Pipeline Stages) Architecture are given below.
Instruction
Instruction Fetch
Register Read
Arithmetic Logic Unit (ALU)
Memory Access
Register Write
Latency
200ps
100ps
200ps
300ps
100ps
(10 pts) What is the clock cycle time in a pipelined and non-pipelined processor?
Pipelined version : ______________
Non-pipelined version : ______________
Instruction
Instruction Fetch
Register Read
Arithmetic Logic Unit (ALU)
Memory Access
Register Write
Latency
200ps
100ps
200ps
300ps
100ps
Explanation / Answer
Pipelined: cycle time determined by slowest stage: 300ps.
Non-pipelined: cycle time determined by sum of all stages: 900ps
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