Write VHDL code to implement a Moore type state machine. The state machine as tw

Question

Write VHDL code to implement a Moore type state machine. The state machine as two outputs, a RESETn input (active low), an ENABLE input (active high) and a CLK input (rising edge triggered). RESETn is an asyn reset that resets the outputs to 00 when low. If RESETn and ENABLE are high, the state machine cycles through a binary count pattern from 00 to 11, then turns back over to 00 and repeats. If RESETn is low the outputs are 00 regardless of the value of ENABLE or CLK edges. Use VHDL state machine design style in notes (http://oi59.tinypic.com/2cwtyjn.jpg).

Explanation / Answer

ENTITY MOORE IS
PORT(A,CLK,RST: IN BIT;
F: OUT BIT); END MOORE;
ARCHITECTURE FSM OF MOORE IS
SUBTYPE STATE_TYPE IS STD_
LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL STATE : STATE_TYPE;
CONSTANT S0:
STATE_TYPE:="001";
CONSTANT S1:
STATE_TYPE:="010";
CONSTANT S2:
STATE_TYPE:="100";
SIGNAL CURRENT_STATE,
NEXT_STATE : STATE_TYPE;
BEGIN
FF: PROCESS (CLK, RST) BEGIN
IF (RST=

Related Questions

Navigate

• Browse (All)
• Browse W
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.