9. Consider the five MIPS pipeline stages discussed on p. 20 of the Chapter 4 le
ID: 3568572 • Letter: 9
Question
9. Consider the five MIPS pipeline stages discussed on p. 20 of the Chapter 4 lecture notes and assume that each pipeline stage completes in 200 ps (the pipeline clock frequency is 5 GHz). Consider these five lw instructions that enter the pipeline with no stalls among them,
1. lw $t0, -8($fp)
2. lw $t1, -12($fp)
3. lw $t2, -16($fp)
4. lw $t3, -20($fp)
5. lw $t4, -24($fp)
(a) How many pipeline clock cycles will it take to execute all five instructions? (b) What is the average CPI for this instruction sequence? (c) What is the average IPC? (d) How much time, in ns, will it take to execute all five instructions. (e) What is the average time, in ps, per instruction? Assume that the clock period of the single-cycle design is 1 ns (the single-cycle clock frequency is 1 GHz). To accurately compare the performance of the pipeline design to the single-cycle design, the number of clocks for each instruction in each design must be the same, so assume that in the single-cycle design a lw completes in 5 singe-cycle clock cycles (this makes it more of a 5-cycle design).
(f) How many single-cycle clock cycles will it take to execute all five instructions? (g) What is the average CPI for
this instruction sequence? (h) What is the average IPC? (i) How much time, in ns, will it take to execute all five
instructions? (j) What is the average time, in ns, per instruction? (k) What is the relative performance of the pipelined design compared to the single-cycle design in this case? (l) How much faster is the pipelined design expressed as a percentage of the single-cycle design?
Explanation / Answer
Solution:
C1
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C9
lw $t0, -8($fp)
IF
ID
EX
MEM
WB
lw $t1, -12($fp)
IF
ID
EX
MEM
WB
lw $t2, -16($fp)
IF
ID
EX
MEM
WB
lw $t3, -20($fp)
IF
ID
EX
MEM
WB
lw $t4, -24($fp)
IF
ID
EX
MEM
WB
a)
Therefore, to complete the five instructions, the pipe line takes 9 clock cycles.
b)
the average CPI for this instruction sequence is:
there are 100 percent of the lw instructions.
Therefore, the CPI value is: 5*100/100=5.
Therefore, the average CPI is: 5/5=1.
c)
The average IPC is,
Here, to complete all the 5 instructions it takes C9 clock cycles.
The instruction per cycle will be 9/5=1.8
Therefore, the IPC is 1.8.
Therefore, the average IPC is (1.8/5)*5=1.8.
d)
To execute each instruction, it takes one pipe line.
Provided each pipe line completes in 200ps.
Where 1ps=0.001ns.
To execute one pipe line, it takes 200*0.001ns
=>0.2 ns.
To execute all the five instructions, it takes 5 pipelines.
To execute all the five instructions it takes 0.2*5ns=1ns.
Therefore, to execute all the five instructions it takes 1ns.
e)
The average time, in ps, per instruction is,
The time taken for each instruction is 200ps.
The time taken for all the 5 instructions is 200ps*5=1000ps.
The average time taken is 1000ps/5=200ps.
f)
Since, it is provided that each instruction it takes 5 single-cycle clock cycles. Here, the number of clock cycles it consumes will be equal to the number of clock cycles the pipe line takes.
Therefore, to complete all the 5 instructions, the single cycle clock takes 9 clock cycles.
g)
the average CPI for this instruction sequence is: 1
Since, there in both the cases the number of cycles it takes is same. So the average CPI for the instruction sequence is 1.
h)
The average IPC is,
Here, to complete all the 5 instructions it takes C9 clock cycles.
The instruction per cycle will be 9/5=1.8
Therefore, the average IPC is (1.8/5)*5=1.8.
i)
To execute each instruction, it takes one pipe line.
Provided each pipe line completes in 1*5=5ns.
To execute all the five instructions, it takes 5 pipelines.
To execute all the five instructions it takes 5*5ns=25ns.
Therefore, to execute all the five instructions it takes 25ns.
j)
The average time, in ps, per instruction is,
The time taken for each instruction is 1ns.
The time taken for all the 5 instructions is 1ns*5=5ns.
The average time taken is 5ns/5=1ns.
k)
To calculate the relative performance, there is no data available related to the latency time. Hence, it cannot be computed.
l)
To execute all the five instructions the pipe line is consuming 1 ns.
Whereas, the single cycle clock is consuming 25ns.
Therefore, the pipe is 0.04 times faster than the single cycle clock.
C1
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C9
lw $t0, -8($fp)
IF
ID
EX
MEM
WB
lw $t1, -12($fp)
IF
ID
EX
MEM
WB
lw $t2, -16($fp)
IF
ID
EX
MEM
WB
lw $t3, -20($fp)
IF
ID
EX
MEM
WB
lw $t4, -24($fp)
IF
ID
EX
MEM
WB
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