(b). Assume a set associative cache mapping as discussed in classs example. Your

Question

(b). Assume a set associative cache mapping as discussed in classs example. Your program will access three memory addresses in the following order: 1,5, 1, 1, 5, 9, 1, 5, 9, 1, 5, 9, 1. How many miss, how many hit? (c). Assume we have a computer where the clocks per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these total 40% of the instructions. If the miss penalty is 25 clock cycles and the miss rate is 4%, how much faster would the computer be if all instructions were cache hits?

Explanation / Answer

b) We will have 9 misses and 4 hits in this order:-

1-Miss

5-Miss

1-Hit

1-Hit

5-Hit

9-Miss

1-Hit

5-Miss

9-Miss

1-Miss

5-Miss

9-Miss

1-Miss

c) If all instructions are cache hits,

Access time = 40*1 = 40 clock cycles

If all instructions are not cache hits,

Access time = 4*26 + 36*1 = 104 + 36 = 140 clock cycles

Time by which CPU becomes faster = 140-40 = 100 clock cycles.

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