Provide the structural and behavioral Verilog design of the following circuit O

Question

Provide the structural and behavioral Verilog design of the following circuit O = S

Provide the structural and behavioral Verilog design of the following circuit O = S'D0 + SD1. Write testbenches and verify from the waveform that they have the same output. Write testbenches for the code modules provided in section C.4 of Appendix C (Figure C.4.1- C.4.3). For simplicity, you can use a 4-bit version of those hardware circuits. Also, feel free to modify the design if you think some component/signal is unnecessary.

Explanation / Answer

//Code Using Strucural Verilog//

module mux(s,D0,D1,O);
input s,D0,D1;
output reg O;
always@ (s,D0,D1)
begin
case(s)// Put the case parameter in brackets
1'b0:O = D0;
1'b1:O = D1;
default :O = 1'b0;
endcase
end
endmodule

//Code Using behavioural Verilog//

module mux(s,D0,D1,O);
input s,D0,D1;
output O;
wire O1,O2,s_not;

and    a1(O1,D0,s_not);
and   a2(O2,D1,s);
or    b1(O,O1,O2);
not   n1(s_not,s);

endmodule

//Code For test bench//

module mux2;

   // Inputs
   reg s;
   reg D0;
   reg D1;

   // Outputs
   wire O;

   // Instantiate the Unit Under Test (UUT)
   mux uut (
       .s(s),
       .D0(D0),
       .D1(D1),
       .O(O)
   );

   initial begin
       // Initialize Inputs
      
   s = 0;
       D0 = 0;
       D1 = 0;

       // Wait 100 ns for global reset to finish
       #10;
       s = 1;
       D0 = 0;
       D1 = 1;
#10;
      
       #10;
       s = 0;
       D0 = 1;
       D1 = 0;
#10;
       s = 1;
       D0 = 0;
       D1 = 0;
       // Add stimulus here

   end
  
endmodule

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