4.3 When processor designers consider a possible improvement to the processor da
ID: 3566632 • Letter: 4
Question
4.3 When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following three problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and 100 ps, respectively, and costs of 1000, 30, 10, 100, 200, 2000, and 500, respectively. Consider the addition of a multiplier to the ALU. This addition will add 300 ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction.
4.3.1 [10]<
Explanation / Answer
Case a:
Compare the cost/performance ratio with and without improvement, then should be follows below calculations:
Consider the following latencies and cost to instructions:
I-Mem
Add
Mux
ALU
Regs
D-Mem
Control
Latency
400 ps
100 ps
30 ps
120 ps
200 ps
350 ps
100 ps
Cost
1000
30
10
100
200
2000
500
Compute total cost:
Cost values of instructions; add total cost of all instruction value is total cost value.
Consider Cost values of instructions are I-Mem, 2 Add units, 3 Mux units, ALU , Regs, D-Mem and Control.
So, the total cost = 3890.
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Compute the speed-up:
Clock cycle time without improvement:
Use to critical data path to find clock cycle time, which for consider latencies ensues to become value for the load instruction. So consider values of instructions from above latencies table for compute clock cycle time without improvement to processor datapath.
Then follows:
Then, the clock cycle time without improvement
=I-Mem + Regs + Mux + ALU + D-Mem+ Mux
= 400 ps + 200 ps + 30 ps + 120 ps + 350ps + 30ps
= 1130 ps
So, without improvement to the processor data path, the clock cycle time is 1130 ps.
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Clock cycle time with improvement:
Consider the following processor improvement table:
Improvement
Latency
Cost
Benefit
Add Multiplier
to ALU
+300 ps for ALU
+600 for ALU
Lets us add MUL instruction. Allows us to execute % fewer instruction (MUL no longer emulated).
Consider improvement to processor data path, observe processor improvement table. In this table, ALU is on the critical data path. Use to critical data path to find clock cycle time, which for consider latencies ensues to become value for the load instruction. So consider values of instructions from above latencies table for compute clock cycle time with improvement to processor data path. Then follows:
Then, the clock cycle time with improvement
=I-Mem + Regs + Mux + ALU + D-Mem+ Mux
= 400 ps + 200 ps + 30 ps + 420 ps + 350ps + 30ps
= 1430 ps
So, with improvement to the processor data path, the clock cycle time is 1430 ps .
I-Mem
Add
Mux
ALU
Regs
D-Mem
Control
Latency
400 ps
100 ps
30 ps
120 ps
200 ps
350 ps
100 ps
Cost
1000
30
10
100
200
2000
500
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