Problem 2: Modify the single-cycle datapath to implement an instruction called \
ID: 3558928 • Letter: P
Question
Problem 2: Modify the single-cycle datapath to implement an instruction called "add to zero" (addz). The "addz"instruction adds two registers and stores the result in a register and also in the memory at address zero. The "addz "instruction takes three registers as operands, for example: addz t0, t1, t2 Like the R-type, (t1+t2) is saved in t0. Also, (t1+t2) is saved in the memory at address zero. (the memory address is always zero for this instruction). This instruction uses the R-type format. The "shamt" and "funct" fields are not used and are filled with zero. a) How can the datapath support this instruction? Mention any new components, wires and modifications and draw them on the attached diagram. b) Give the values of all the control signals for the addz instruction.
Explanation / Answer
it can be done in 3 clock cycles.
1. fetch the instructions from the ccm/ram
2. decode the instruction and check whether it is addz or not.
3. pass the operans to the ALU along the Muxes datapath shown in the figure. The ALU will calculate the result in one clock cycle and writeback the same result.
no additional hardware is required to implement this instruction as it just requires swapping the operands.
no change in control signals as well.
Do it as if you donot need any wire
total 6 clock cycle.
1. FI (Fetch Instruction) - Fetch Instruction from RAM
2. FO (Fetch Operand) - Fetch the operands if have
3. DI (Decode Instruction) - Decode the Instruction
4. EI (Execute Instruction) - Execute Instruction
Now this is the important step.
In this phase we will implement Two Instructions
a. ADD t1 + t2 t0
b. str t0 0
For this we will
5. CO(Calculate operand) - Calculate operand address that is t1, t2 and t0
6. WB(Write Back) - Write Back to Memory by storing operation at zero adress.
Else add an instruction for addz in multepexerr through wire. It will also take 6 clock cycle.
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