Q2. For the following we consider instruction encoding for instruction set Archi

Question

Q2. For the following we consider instruction encoding for instruction set Architectures. a) Consider the case of a processor with an instruction length of 12 bits and with 32 general purpose registers so the size of the address fields is 5 bits. Is it possible to have instruction encoding for the following: 3 two- address instructions 30 one address instructions 45 zero address instructions b) Assuming the same instruction length and address field sizes as above, determine if it is possible to have 3 two- address instructions 31 one address instructions 35 zero address instructions

Explanation / Answer

I have given the answer of the each part with expalnation

1.3 two address instructions: No Since each address is of 5 bits and we need two address instructions so we need twobits for three addresses and 5*2=10 bits for indivisual addresses since this exceeds the no pf bits provided hence itis not possible.

2. 30 one address instructions : we need 5 bits for 30 instructions and 5 bits for the address field. Since it requires 10 bits hence it is possible.

3. 45 zero address instructions : we need 6 bits for 45 addresses So it is possible.

4. 3 two-address instructions : answer is the same as the 1

5. 31 one address instructions:  we need 5 bits for 31 instructions and 5 bits for the address field. Since it requires 5*2=10 bits hence it is possible.

6.  35 zero address instructions : we need 6 bits for 35 addresses So it is possible.

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