Question 1 Which of the following flip-flop timing parameters indicates the time

Question

Question 1

Which of the following flip-flop timing parameters indicates the time it takes a Q output to respond to an input?

Question 1 options:

tw(1), tw(h)

fmax

ts, th

tphl, tplh

Question 2

Asynchronous flip-flop preset and clear inputs generally:

Question 2 options:

cause the outputs to change states depending on the SR, JK, or similar controlling inputs.

cause the outputs to change states as soon as the input clock makes the desired transition.

clear the inputs so the flip-flop can start over.

act as manual overrides that cause the outputs to change states regardless of the inputs or clock transitions.

Question 3

The setup time of a clocked flip-flop is:

Question 3 options:

the maximum amount of time that an output must remain stable after an active clock transition.

the minimum amount of time that an output must remain stable before an active clock transition.

the minimum amount of time that an input must remain stable before an active clock transition.

the minimum amount of time that an input must remain stable after an active clock transition.

Question 4

The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle indicates:

Question 4 options:

the FF is level active and can only change states when the CLOCK = 1.

the FF is edge-triggered and can only change states when the clock goes from 1 to 0.

the FF is an active LOW device and can only change states when the CLOCK = 0.

the FF is edge-triggered and can only change states when the clock goes 0 to 1.

Question 5

A negative-edge-triggered J-K flip-flop is presently in the CLEAR state. Which of the following input conditions will cause it to change states?

Note:

PGT: Clock transition from '0' to '1'

NGT: Clock transition from '1' to '0'

Question 5 options:

CLK = PGT, J = 1, and K = 0

CLK = PGT, J = O, and K = 1

CLK = NGT, J = O, and K = 1

CLK = NGT, J = 1, and K = 0

Question 6

The difference between a D-latch and an edge-triggered D-type flip-flop is that the latch:

Question 6 options:

always "latches" the Q output to the D input regardless of other inputs.

is controlled by the logic level at its ENABLE input rather than a CLK transition.

always "latches" the Q output to the complement of the D input regardless of other inputs.

triggers on either the rising or falling edge of an ENABLE signal rather than the CLK input logic level.

Question 7

The preset and clear inputs to a J-K flip-flop are HIGH (1). Which of the following is true?

Question 7 options:

The Q output is immediately set to 1.

The flip-flop is free to respond to its J, K, and clock inputs.

The Q output is in an ambiguous state.

The Q output is immediately cleared.

Question 8

What is one disadvantage of an R-S flip-flop?

Question 8 options:

It has no Enable input.

It has only a single output.

It has an invalid state.

It has no CLOCK input.

Question 9

If both inputs of an S-R flip-flop are low, what will happen when the clock goes high?

Question 9 options:

An invalid state will exist.

No change will occur in the output.

The output will reset.

The output will toggle.

Suppose that the in the circuit above the propagation delay of the inverter is 1.5 ns and the propagation delay and settup times of the flip-flop are 3.5 ns and 2 ns respectively. What is the shortest clock period for the circuit that will not violate the time constraints?

Question 10 options:

3.5 ns

5.5 ns

8 ns

None of the above

Question 11

When both inputs of a J-K pulse-triggered FF are high, and the clock cycles, the output will ________.

Question 11 options:

be invalid

remain unchanged

not change

toggle

Question 12

What would be the output of a JK Flip-Flop (assume 74LS112) at the end if J=1 and K=0 for one clock pulse and then J=1 and K=1 for the next 3 clock pulses? Assume that PS and CLR are both 1.

Question 12 options:

0

1

Question 13

The figure above shows a S-R circuit and the the corresponding waveform for the inputs S and R. What are the values of the output Q for times t1, t2, t3 and t4 respectively?

Question 13 options:

0,1,1,0

1,0,0,1

1,1,0,0

0,0,1,1

Question 14

For the circuit of the figure above, if the circuit is fed with the waveform given, what are the values of Q for times t1,t2 and t3 respectively?

Question 14 options:

Question 15

The figure above shows a waveform for the inputs of a JK flip-flop rise-edge-triggering. What are the values of the flip-flop output for the times shown in b,d,f,h and j respectively?

Question 15 options:

0, 1, 0, 1, 1

0, 1, 1, 1, 0

0, 0, 1, 1, 0

Nonoe of the above

Question 16

The figure above shows a waveform for the inputs of a JK flip-flop falling-edge-triggering with PRESET and CLEAR. What are the values of the flip-flop output for the times shown in c, g, i, k and o respectively?

Question 16 options:

0, 0, 1, 1, 1

0, 1, 1, 1, 0

0, 1, 1, 0, 1

None of the above

Question 17

The table given above shows some parameters for the a 7474 Edge Triggered D Flip-Flop. Which of the following circuit parameters would be most likely to limit the maximum operating frequencythis type of flip-flop?

Question 17 options:

Low-to-High Propagation delay time

High-to-Low Propagation delay time

Set-up time

Hold time

Question 18

The table given above shows some parameters for the a 7474 Edge Triggered D Flip-Flop. What would be the maximum operating frequency this type of flip-flop?

Question 18 options:

15.38 MHz

16.66 MHz

22.22 MHz

40 MHz

Question 19

For the circuit shown what are the values of Q for times t0,t1,t2 respectively?

Assume Q=0 initially.

Question 19 options:

1 1 1

0 0 0

0 1 0

0 0 1

None of the above

tw(1), tw(h)

fmax

ts, th

tphl, tplh

Explanation / Answer

1.ts, th

2.act as manual overrides that cause the outputs to change states regardless of the inputs or clock transitions.

3.the minimum amount of time that an input must remain stable before an active clock transition.

4.the FF is edge-triggered and can only change states when the clock goes 0 to 1.

5.CLK = NGT, J = 1, and K = 0

6.triggers on either the rising or falling edge of an ENABLE signal rather than the CLK input logic level.

7.The flip-flop is free to respond to its J, K, and clock inputs.

8.It has an invalid state.

9.No change will occur in the output.

10.3.5 ns

11.0

12.0

13.0,0,1,1

14.0,0,0

15.0, 1, 1, 1, 0

16.0, 0, 1, 1, 1

17.High-to-Low Propagation delay time

18.16.66 MHz

19.0,1,0

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