DeMorgan\'s Theorem is . If Q = 0, R = 1 and S = 1, what is If X = 1 and Y = 0,

Question

DeMorgan's Theorem is

.

If Q = 0, R = 1 and S = 1, what is

If X = 1 and Y = 0, what is (X + Y)'?

Any binary number can be converted to a decimal number. A) True
B) False
2. The MSB is typically the rightmost bit in a binary number. A) True
B) False
3. Chip pinouts and signal definitions can be found in a manufacturer's data sheet. A) True
B) False
4. Period is the number of times that a periodic waveform repeats per second. A) True
B) False
5. The Leading Edge of a signal is the edge of the pulse occurring after the Initial Edge. A) True
B) False
6.

DeMorgan's Theorem is

.

A) True
B) False
7. AND gates take precedence over OR gates. A) True
B) False
8.

A) True
B) False
9. The Altera software assumes that active LOW asynchronous CLEAR and SET inputs are tied high; therefore, to make them inactive, the user can leave them open. A) True
B) False
10. In a gray code, each number is 3 greater than the binary representation of that number. A) True
B) False
11. The duty cycle of a periodic waveform is ____. A) the time the signal is HIGH
B) the number of times the waveform repeats in one second
C) the fraction of the period that the signal is in the HIGH state
12. The falling edge of a signal is: A) the transition from 1 to 0
B) the transition from 0 to 1
C) the stable value after the signal reaches logic 0
13. A logic circuit whose output is LOW when at least one input is HIGH is ____. A) AND gate
B) NOR gate
C) NAND gate
14. The family of logic whose family is composed of bipolar junction transistors is ____. A) CMOS
B) TTL
C) BJT
15. A binary number's value changes most drastically when the ____ is changed. A) MSB
B) frequency
C) duty cycle
16. Convert the binary number 1011010 to hex: A) 510
B) 5A
C) 90
17. Convert the decimal number 64206 to hex: A) E9BD
B) FACE
C) 9F8
18. Which hexadecimal number is after hexadecimal number 369? A) 370
B) 400
C) 36A
19. Which of the following applications is best suited for the OR logic function? A) Enabling a security system requires a key in an operator console and a main controller at the same time.
B) A ride at a theme park requires that the car hits a sensor while the operator holds down an ENABLE button
C) A machine has a hand button and a foot switch which must be depressed to operate the machine.
D) A bank alarm will trigger when any of the tellers hits a panic button.
20. If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n) ____. A) AND
B) OR
C) NAND
21. Karnaugh maps for functions with 4 variables have how many cells? A) 4
B) 8
C) 16
D) 40
22. The process of building a circuit from a description such as a Boolean equation or truth table is ____. A) Karnaugh mapping
B) gating
C) synthesis
D) analysis
23. Convert 170 (decimal) to binary. A) 10101010
B) 1010
C) 10
24. Convert 11001001 (binary) to decimal. A) 201
B) 102
C) 202
25. If the inputs to an EXCLUSIVE-NOR gate are 1 and 0, what is the output? A) 1
B) 0
C) 10
26. What is the answer to A + B + C if A = 1, B = 0, and C = 0? A) 1
B) 0
27.

If Q = 0, R = 1 and S = 1, what is

   ?

A) 1
B) 0
28.

If X = 1 and Y = 0, what is (X + Y)'?

A) 0
B) 1
29. Convert the hexadecimal number 5A5F to binary. A) 10101111
B) 101101001011111
C) 101101111111
30. The condition occurring when the addition of 2 positive numbers yields an apparent negative result, or 2 negative numbers yields an apparent positive result is called ____________________. A) Overflow
B) Gray Code
C) Master reset
31. A binary code where one entry varies from the previous entry by one bit is called _________________________. A) Overflow
B) Gray code
C) Master reset
32. An asynchronous input setting on a sequential circuit to a known value, usually zero, is called _________________________. A) Overflow
B) Gray code
C) Master reset
33. A table showing every possible input condition for every possible transition of sequential counter is the ____________________ table A) Excitation
B) Structural Design
C) Gray code
34. A design methodology connecting predefined components together to form a circuit is ______________________________. A) Excitation
B) Structural Design
C) Overflow

Explanation / Answer

1.A

2.B

3.A

4.B

5.A

6.A

7.B

8.A

9.B

10.B

11.C

12.A

13.B

14.B

15.A

16.B

17.B

18.C

19.D

20.C

21.C

22.C

23.A

24.A

25.B

26.A

27.A

28.A

29.B

30.A

31.B

32.C

33.A

34.B

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